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68073 Commits

Author SHA1 Message Date
Evan Quan
26ef32518a drm/amd/powerplay: maximize code sharing between .hw_init and .resume 
Then redundant code can be dropped.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
4e8cb0c011 drm/amd/powerplay: move those operations not needed for resume out 
Since smu_smc_table_hw_init() is needed for both .hw_init and .resume.
By doing this, we can drop unnecessary operations on resume.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
02cf91c113 drm/amd/powerplay: postpone operations not required for hw setup to late_init 
So that we do not need to perform those unnecessary operations again on
resume.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
792f80d192 drm/amd/powerplay: clean up the overdrive settings 
Eliminate the buffer allocation and drop the unnecessary
overdrive table uploading.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
4a13b4cefc drm/amd/powerplay: clean up the APIs for pptable setup 
Combine and simplify the logics for setup pptable.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
12ea344941 drm/amd/powerplay: clean up the APIs for bootup clocks 
Combine and simplify the logics for retrieving bootup
clocks.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
78eb4a3615 drm/amd/powerplay: centralize all buffer allocation in sw_init phase 
To fit common design. And this can simplify the buffer deallocation.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
61555ccbf9 drm/amd/powerplay: implement a common API for dpms disablement 
So that code can be shared between .hw_fini and .suspend.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
2f55c26443 drm/amd/powerplay: drop unused APIs and unnecessary checks 
Minor code cleanups.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Evan Quan
3115734125 drm/amd/powerplay: eliminate asic type check 
The macros check if the asic has the callback.
So no need to explicitly check.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Colin Ian King
5402eb5ee5 drm/amd/display: fix spelling mistake: "propogation" -> "propagation" 
There is a spelling mistake in a dml_print message. Fix it.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Alex Deucher
3a3a720eb3 drm/amdgpu/display: use blanked rather than plane state for sync groups 
We may end up with no planes set yet, depending on the ordering, but we
should have the proper blanking state which is either handled by either
DPG or TG depending on the hardware generation.  Check both to determine
the proper blanked state.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
Fixes: 5fc0cbfad4 ("drm/amd/display: determine if a pipe is synced by plane state")
Cc: nicholas.kazlauskas@amd.com
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Nicholas Kazlauskas
4ec6c0a208 drm/amd/display: Revalidate bandwidth before commiting DC updates 
[Why]
Whenever we switch between tiled formats without also switching pixel
formats or doing anything else that recreates the DC plane state we
can run into underflow or hangs since we're not updating the
DML parameters before committing to the hardware.

[How]
If the update type is FULL then call validate_bandwidth again to update
the DML parmeters before committing the state.

This is basically just a workaround and protective measure against
update types being added DC where we could run into this issue in
the future.

We can only fully validate the state in advance before applying it to
the hardware if we recreate all the plane and stream states since
we can't modify what's currently in use.

The next step is to update DM to ensure that we're creating the plane
and stream states for whatever could potentially be a full update in
DC to pre-emptively recreate the state for DC global validation.

The workaround can stay until this has been fixed in DM.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Alex Deucher
730c2eb977 drm/amdgpu/fence: use the no_scheduler flag 
Rather than checking the ring type manually.  We already set
this for MES and KIQ (and a few other special cases).

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Alex Deucher
eb0b5d6fdb Revert "drm/[radeon|amdgpu]: Replace one-element array and use struct_size() helper" 
This reverts commit 4541ea81ed.

This changes structs used by the hardware and breaks dpm on some cards.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Nicholas Kazlauskas
f86c9b8b56 drm/amd/display: Only actually breakpoint if DEBUG_KERNEL_DC is enabled 
To match previous behavior and to not hang the kernel if someone
accidentally builds with KGDB enabled.

Fixes: 1aad707819 ("drm/amd/display: Make BREAK_TO_DEBUGGER() a debug print")

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Huang Rui
da483dd1d8 drm/amd/powerplay: use existed smu_dpm_set* interfaces to implement powergate functions 
Abstract powergate_vcn/jpeg functions, using smu_dpm_set* to implement it.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:16 -04:00
Tianci.Yin
cc375d8c52 drm/amdgpu: temporarily read bounding box from gpu_info fw for navi12 
The bounding box is still needed by Navi12, temporarily read it from gpu_info
firmware. Should be droped when DAL no longer needs it.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
96134346bb drm/amd/display: Add DCN3 to Kconfig 
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
e77165bf7b drm/amd/display: Add DCN3 blocks to Makefile 
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Alex Deucher
cb8bcc9825 drm/amdgpu/display: fix build without CONFIG_DRM_AMD_DC_DCN3_0 
Need to guard some new DCN3.0 stuff.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Dmytro Laktyushkin
f0bfa78b0f drm/amd/display: fix and simplify pipe split logic for DCN3 
This was done already done for other DCN blocks.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
464ab91ac5 drm/amdgpu: Enable DM block for DCN3 
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
7f3e2919c9 drm/amd/display: Remove Unused Registers 
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
fb625e1b65 drm/amd/display: Handle RGBE_ALPHA Pixel Format 
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
c5c76abd49 drm/amd/display: Init function tables for DCN3 
Initilize function tables for hw programing

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
3c10f4fb90 drm/amd/display: Add DCN3 VPG 
Video Package generator.

used to prepare avi info, DP info etc

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
73de3de5bc drm/amd/display: Add DCN3 AFMT 
Audio formating

Audio related code for setup/control

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
330fa233f8 drm/amd/display: Add DCN3 Command Table Helpers 
-Handle DCN3 cases for bios parser and command tables
-Add command function tables for DCN3

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
5dba4991fd drm/amd/display: Add DCN3 Resource 
Add support for managing resources for DCN3

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
790373245e drm/amd/display: Add DCN3 Support in DM (v2) 
Handle DCN3 in amdgpu_dm

v2: fix num_pkrs handling

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
d99f13878d drm/amd/display: Add DCN3 HWSEQ 
Add HW sequence programing for DCN3

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
5baebf61ba drm/amd/display: Add DCN3 DMUB 
DMUB (Display Micro-Controller Unit)

Used to read/write regs

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
666ed8bfd1 drm/amd/display: Add DCN3 GPIO 
Add support to program GPIO HW block

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
21f4809ae4 drm/amd/display: Add DCN3 IRQ 
Add IWQ services for DCN3,

This allows us to create/init and manage irqs for DCN3

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Bhawanpreet Lakha
6725a88f88 drm/amd/display: Add DCN3 DML 
Add support for DML(Display mode library) for bandwidth calculations

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
8993dee0de drm/amd/display: Add DCN3 DWB 
Add support to program the DCN3 DWB (Display Writeback)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
4898dc4847 drm/amd/display: Add DCN3 MMHUBHUB 
Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
db7b0216c4 drm/amd/display: Add DCN3 HUBP 
Add support to program the DCN3 HUBP (Display to data fabric interface
pipe)

HW Blocks:

 +--------++------+
 | HUBBUB || HUBP |
 +--------++------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
8f712e3e5e drm/amd/display: Add DCN3 HUBHUB 
Add support to program the HUBBUB (DCN memory HUB interface)

HW Blocks:

 +--------+
 | HUBBUB |
 +--------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
03f54d7d34 drm/amd/display: Add DCN3 DPP 
Add support to program the DCN3 DPP (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
b708205f08 drm/amd/display: Add DCN3 MPC 
Add support to program the DCN3 MPC (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
8ea13e52a5 drm/amd/display: Add DCN3 OPP header 
Add support to program the DCN3 OPP (Output Plane Processing)

HW Blocks:

    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
64e7f91e7a drm/amd/display: Add DCN3 OPTC 
Add support for programming the DCN3 OPTC (Output Timing Controller)

HW Blocks:

    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
2a3a0d5d79 drm/amd/display: Add DCN3 DCCG 
Add programming of the DCCG (Display Controller Clock Generator)
block:

HW Blocks:

    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
4d55b0dd1c drm/amd/display: Add DCN3 CLK_MGR 
Adds support for handling of clocking relevant to the DCN3 block

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
be547111d2 drm/amd/display: Add DCN3 DIO 
Add support for the DIO (Display IO)  block of DCN3, which entails our
stream and link encoders.

HW Blocks:

    +--------+
    |  DIO   |
    +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Bhawanpreet Lakha
7c40270be7 drm/amd/display: Add DCN3 chip ids 
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Likun Gao
2c6e83a134 drm/amdgpu: bypass tmr when reserve c2p memory 
C2P memory reserved should not in tmr memory range.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00
Likun Gao
72d208c23c drm/amdgpu: remove unnecessary check for mem train 
a.Check whether mem train support when try to reserve related memory.
b.Remove ASIC check and atom firmware table version check as the check
of firmware capability is enough to achieve that purpose.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:14 -04:00