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67543 Commits

Author SHA1 Message Date
Jiansong Chen
cf4554fada drm/amdgpu: support athub cg setting for navy_flounder 
navy_flounder has athub ip v2.1.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:25 -04:00
Jiansong Chen
40582e670f drm/amdgpu: enable GFX clock gating for navy_flounder 
Enable GFX MGCG, CGCG and 3DCG for navy_flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:21 -04:00
Boyuan Zhang
00740df995 drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounder 
Enable JPEG3.0 PG and CG for navy_flounder by setting up the flags to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:17 -04:00
Boyuan Zhang
c6e9dd0ea8 drm/amdgpu: enable VCN3.0 DPG for navy_flounder 
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:14 -04:00
Boyuan Zhang
ebb06097ee drm/amdgpu: enable VCN3.0 PG and CG for navy_flounder 
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:12 -04:00
Jiansong Chen
c5b6c914d2 drm/amdgpu: enable cp_fw_write_wait for navy_flounder 
It's the same with sienna_cichlid, cp fw for navy_flounder
can support WAIT_REG_MEM packet.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:09 -04:00
Boyuan Zhang
290b4ad592 drm/amdgpu: add vcn ip block for navy_flounder 
Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:06 -04:00
Boyuan Zhang
5cc07534d8 drm/amdgpu: add navy_flounder vcn firmware support 
Add navy_flounder to vcn family

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:04 -04:00
Jiansong Chen
41e3b1c13f drm/amdgpu/gfx10: add gc golden setting for navy_flounder 
Add gc golden setting for navy_flounder

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:02 -04:00
Chengming Gui
09759e13f4 drm/amdkfd: Add kfd2kgd_funcs for navy_flounder kfd support 
Add callbacks to KGD for navy flounder.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:59 -04:00
Chengming Gui
de89b2e456 drm/amdkfd: Support navy_flounder KFD 
Add KFD support for Navy Flounder.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:55 -04:00
Jiansong Chen
f081e6971b drm/amdgpu: use front door firmware loading for navy_flounder 
Same as other navi asics.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:52 -04:00
Jiansong Chen
7420eab23b drm/amdgpu: add psp block for navy_flounder 
Add psp and smu block for navy_flounder with
psp firmware load type.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:50 -04:00
Jiansong Chen
c82b38ec2e drm/amdgpu: add psp support for navy_flounder 
Currently skip ASD FW loading and ih reroute per
sienna_cichlid.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:47 -04:00
Jiansong Chen
f4497d1029 drm/amdgpu: add smu block for navy_flounder 
Add SMU block for navy_flounder with direct
firmware load type.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:44 -04:00
Jiansong Chen
82121d154a drm/amdgpu/powerplay: add smu support for navy_flounder 
Now navy_flounder will reuse the smu11 driver_if header and ppt
functions for sienna_cichlid. Later navy_flounder can maintain
its own version if the compatibility is broken.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:41 -04:00
Jiansong Chen
922783755b drm/amdgpu: add gmc cg support for navy_flounder 
The athub version used for navy_flounder is v2.1.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:38 -04:00
Jiansong Chen
8f8463dddc drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounder 
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2, and navy_flounder has the same gfx10.3 IP
with sienna_cichlid.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:35 -04:00
Tao Zhou
c4a8b80286 drm/amdgpu: configure navy_flounder gfx according to gfx 10.3 
The gfx version of navy_flounder is 10.3, identical to
sienna_cichlid, follow the way of sienna_cichlid.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:33 -04:00
Jiansong Chen
5404f07359 drm/amdgpu: add virtual display support for navy_flounder. 
Virtual display support for bring up and virtualization.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:29 -04:00
Jiansong Chen
df2d15df04 drm/amdgpu: add sdma ip block for navy_flounder 
Navy_Flounder has the same sdma IP version with
sienna_cichlid, and it has 2 sdma controllers.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:26 -04:00
Jiansong Chen
885eb3fad6 drm/amdgpu: add gfx ip block for navy_flounder 
since navy_flounder has similar gc IP version with
sienna_cichlid, follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:23 -04:00
Jiansong Chen
026c396b41 drm/amdgpu: add ih ip block for navy_flounder 
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:19 -04:00
Jiansong Chen
fc8f07da1f drm/amdgpu: add gmc ip block for navy_flounder 
navy_flounder has similar gc IP version with sienna_cichlid,
follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:14 -04:00
Jiansong Chen
8515e0a489 drm/amdgpu: add common ip block for navy_flounder 
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:11 -04:00
Jiansong Chen
f097ff15cd drm/amdgpu: add support on mmhub for navy_flounder 
navy_flounder has the same mmhub IP version with sienna_cichlid,
follow its setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:09 -04:00
Jiansong Chen
c8c959f601 drm/amdgpu: initialize IP offset for navy_flounder 
since navy_flounder has the same ip offset with sienna_cichlid,
follow sienna_cichlid setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:07 -04:00
Jiansong Chen
543aa2595c drm/amdgpu/soc15: add support for navy_flounder 
Add soc support.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:00 -04:00
Jiansong Chen
d463d8c964 drm/amdgpu/gfx10: add clockgating support for navy_flounder 
Same as navi10.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:58 -04:00
Jiansong Chen
0287ac57b5 drm/amdgpu/gmc10: add navy_flounder support 
Same as navi10.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:53 -04:00
Jiansong Chen
6501019304 drm/amdgpu/gfx10: add support for navy_flounder firmware 
Declare the gfx/compute firmwares.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:50 -04:00
Jiansong Chen
41f446bf52 drm/amdgpu: set asic family and ip blocks for navy_flounder 
Add the asic family and IP blocks for navy flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:48 -04:00
Jiansong Chen
47eb83d9a6 drm/amdgpu: set fw load type for navy_flounder 
Currently navy_flounder only supports backdoor loading type.
Will switch to psp load type when psp is ready.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:45 -04:00
Jiansong Chen
120eb83336 drm/amdgpu: add navy_flounder gpu info firmware 
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:43 -04:00
Jiansong Chen
ddd8fbe77d drm/amdgpu: add navy_flounder asic type 
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:39 -04:00
Huang Rui
6565547113 drm/amdgpu: expand to add multiple trap event irq id 
Sienna_cichlid has four sdma instances, but other chips don't.
So we need expand to add multiple trap event irq id in sdma
v5.2.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:35 -04:00
Jack Zhang
c8466cc0d2 drm/amd/sriov skip vcn powergating and dec_ring_test 
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.

2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.

V2: delete unneccessary white lines and refine implementation.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:28 -04:00
John Clements
a330272936 drm/amdgpu: correct ta header v2 ucode init start address 
resolve bug calculating fw start address within binary

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:18 -04:00
Jack Zhang
1f61a43fce drm/amd/sriov porting sriov cap to vcn3.0 
1.In early_init and for sriov, hardcode
  harvest_config=0, enc_num=1

2.sw_init/fini
  alloc & free mm_table for sriov
  doorbell setting for sriov

3.hw_init/fini
  Under sriov, add start_sriov to config mmsch
  Skip ring_test to avoid mmio in VF, but need to initialize wptr for vcn rings.

4.Implementation for vcn_v3_0_start_sriov

V2:Clean-up some uneccessary funciton declaration.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:11 -04:00
Jack Zhang
7ddb4d6c43 drm/amd/sriov add mmsch_v3 interface 
For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch
to set the World Switch for MM appropriately. This patch add
the interface for mmsch_v3.0.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:05 -04:00
Jack Zhang
fc30e840dc drm/amdgpu: optimize rlcg write for gfx_v10 
For gfx10 boards, except for nv12, other boards take mmio write
rather than rlcg write

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:59 -04:00
Jack Zhang
c45fbe1bd5 drm/amd/sriov skip jped ip block and close pgcg flags 
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:53 -04:00
Evan Quan
3cd7e415ae drm/amd/powerplay: drop unused code around thermal range setting 
Leftover of previous cleanups.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:46 -04:00
Evan Quan
1e1964b777 drm/amd/powerplay: maximum the code sharing on thermal irq setting 
Put the common code in smu_v11_0.c instead of having one copy each.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:40 -04:00
Evan Quan
0540ecedcb drm/amd/powerplay: sort the call flow on temperature ranges retrieving 
This can help to maintain clear code layer.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:32 -04:00
Evan Quan
e02e4d513e drm/amd/powerplay: cache the software_shutdown_temp 
As it's needed in the succeeding thermal irq setting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:24 -04:00
Evan Quan
2b1f12a2da drm/amd/powerplay: correct Sienna Cichlid temperature limit settings 
These are needed for temp1/2/3 related hwmon interfaces.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:18 -04:00
Evan Quan
cbf3f132fe drm/amd/powerplay: correct Navi1X temperature limit settings 
These are needed for temp1/2/3 related hwmon interfaces.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:09 -04:00
Evan Quan
0b590970a5 drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount 
The LCLK dpm table setup should be performed in .update_pcie_parameters().
Otherwise, the updated GenSpeed and LaneCount information will be lost.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:59 -04:00
Evan Quan
778f8e6afe drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting 
This can also help to maintain clear code layer.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:54 -04:00