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132 Commits

Author SHA1 Message Date
Likun Gao
f2e2573c08 drm/amdgpu: use mode1 reset by default for sienna_cichlid 
Swith default gpu reset method for sienna_cichlid to MODE1 reset.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-07 17:47:25 -04:00
John Clements
ebfbd1c2ca drm/amdgpu: expand sienna chichlid reg access support 
Added dedicated 64bit reg read/write support

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-06 16:23:20 -04:00
John Clements
c652923afa drm/amdgpu: enable xgmi support for sienna cichlid 
set xgmi support flag suring nv ip init sequence

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:39 -04:00
Jiansong Chen
85e7151baa drm/amdgpu: enable ih CG for navy_flounder 
Enable ih CG by setting the corresponding flag.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
4759f8871f drm/amdgpu: enable hdp CG and LS for navy_flounder 
Enable hdp CG and LS by setting the corresponding flags.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
92c737561c drm/amdgpu: enable mc CG and LS for navy_flounder 
Enable mc CG and LS by setting the corresponding flags.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
47fc894a87 drm/amdgpu: enable athub/mmhub PG for navy_flounder 
Enable athub/mmhub PG by setting the corresponding flags.
Actually the enablement is exercised by PMFW.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Bhawanpreet Lakha
a6c5308f2a drm/amd/display: add DC support for navy flounder 
Plumb DC support for navy flounder through.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:26 -04:00
Jiansong Chen
40582e670f drm/amdgpu: enable GFX clock gating for navy_flounder 
Enable GFX MGCG, CGCG and 3DCG for navy_flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:21 -04:00
Boyuan Zhang
00740df995 drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounder 
Enable JPEG3.0 PG and CG for navy_flounder by setting up the flags to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:17 -04:00
Boyuan Zhang
c6e9dd0ea8 drm/amdgpu: enable VCN3.0 DPG for navy_flounder 
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:14 -04:00
Boyuan Zhang
ebb06097ee drm/amdgpu: enable VCN3.0 PG and CG for navy_flounder 
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:12 -04:00
Boyuan Zhang
290b4ad592 drm/amdgpu: add vcn ip block for navy_flounder 
Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:06 -04:00
Jiansong Chen
7420eab23b drm/amdgpu: add psp block for navy_flounder 
Add psp and smu block for navy_flounder with
psp firmware load type.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:50 -04:00
Jiansong Chen
f4497d1029 drm/amdgpu: add smu block for navy_flounder 
Add SMU block for navy_flounder with direct
firmware load type.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:44 -04:00
Jiansong Chen
5404f07359 drm/amdgpu: add virtual display support for navy_flounder. 
Virtual display support for bring up and virtualization.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:29 -04:00
Jiansong Chen
df2d15df04 drm/amdgpu: add sdma ip block for navy_flounder 
Navy_Flounder has the same sdma IP version with
sienna_cichlid, and it has 2 sdma controllers.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:26 -04:00
Jiansong Chen
885eb3fad6 drm/amdgpu: add gfx ip block for navy_flounder 
since navy_flounder has similar gc IP version with
sienna_cichlid, follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:23 -04:00
Jiansong Chen
026c396b41 drm/amdgpu: add ih ip block for navy_flounder 
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:19 -04:00
Jiansong Chen
fc8f07da1f drm/amdgpu: add gmc ip block for navy_flounder 
navy_flounder has similar gc IP version with sienna_cichlid,
follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:14 -04:00
Jiansong Chen
8515e0a489 drm/amdgpu: add common ip block for navy_flounder 
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:11 -04:00
Jiansong Chen
c8c959f601 drm/amdgpu: initialize IP offset for navy_flounder 
since navy_flounder has the same ip offset with sienna_cichlid,
follow sienna_cichlid setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:07 -04:00
Jiansong Chen
543aa2595c drm/amdgpu/soc15: add support for navy_flounder 
Add soc support.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:00 -04:00
Jack Zhang
c45fbe1bd5 drm/amd/sriov skip jped ip block and close pgcg flags 
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:53 -04:00
Wenhui Sheng
273da6ff7c drm/amdgpu: add module parameter choose reset mode 
Default value is auto, doesn't change
original reset method logic.

v2: change to use parameter reset_method
v3: add warn msg if specified mode isn't supported

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:42:01 -04:00
Wenhui Sheng
311531f087 drm/amdgpu: enable mode1 reset 
For sienna cichlid, add mode1 reset path for sGPU.

v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1
v3: split emergency restart logic to a new patch

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:41:54 -04:00
Likun Gao
1b0443b115 drm/amdgpu: fix coding error of mmhub pg enablement 
MMHUB powergating should be disabled on navi12 and enabled on sienna
cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-08 09:01:24 -04:00
Wenhui Sheng
c1299461b7 drm/amdgpu: request init data in virt detection 
Move request init data to virt detection func, so we
can insert request full access between request init data
and set ip blocks.

Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-02 12:02:50 -04:00
Bhawanpreet Lakha
464ab91ac5 drm/amdgpu: Enable DM block for DCN3 
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:15 -04:00
Boyuan Zhang
d00b0fa90f drm/amdgpu: enable DPG mode for VCN3.0 
Enable DPG mode for VCN3.0 by updating related flag.

V2: update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Kenneth Feng
846938c223 drm/amd/powerplay: enable mmhub pg 
mmhub pg can be obvserved from PCTL_CTRL

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Kenneth Feng
b794616d1f drm/amd/powerplay: enable athub pg 
enable athub pg and the status can be checked in
ATHUB_MISC_CNTL.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
shaoyunl
38d5bbef5d drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOV 
SMU firmware already been loaded from host, don't enable it for now.
May need to re-work it if we want to enable the SMU for guest in the future.

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Likun Gao
98f8ea29ff drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid. 
Enable mmhub clockgating.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
bcc8367f94 drm/amd/amdgpu: add athub ls support 
athub ls is bounded with hdp ls,verified.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
3a32c25a8e drm/amd/amdgpu: add IH cg support 
IH cg verified

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
ca36461f42 drm/amd/amdgpu: add HDP mgcg and ls support 
add HDP mgcg and ls support and verified

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
91c6adf873 drm/amd/amdgpu: fix the HDP LS/DS/SD programming 
confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN
have to be set for SRAM LS/DS/SD

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
00194def45 drm/amdgpu: open GFX clock gating for sienna_cichlid 
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Leo Liu
4d72dd12f0 drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid 
By adding JPEG HW block to Sienna_Cichlid

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b467c4f5b4 drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid 
By setting up the flags to the ASIC

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b8f10585cb drm/amdgpu: enable VCN3.0 for Sienna_Cichlid 
By adding VCN HW block to Sienna_Cichlid

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
e823be13db drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid 
By setting up the flags to the ASIC

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Jack Xiao
a346ef86a9 drm/amdgpu: add mes block to sienna_cichlid 
Add mes block support to sienna_cichlid.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Jack Xiao
2051923272 drm/amdgpu: assign the doorbell index to mes ring 
MES ring will use the assigned doorbell index for
command submission.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
56304e72af drm/amdgpu: add psp block load condition for sienna_cichlid 
Enable PSP block for firmware loading and other security
setup only when amdgpu use PSP load type to load ucode.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
5aa023506a drm/amdgpu: enable psp ip block for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
b07e5c60e4 drm/amdgpu/powerplay: add smu block for sienna_cichlid 
Add SMU block for sienna_cichlid with psp load type.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:58:55 -04:00
Likun Gao
9a98676007 drm/amdgpu: add virtual display support for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:05 -04:00
Likun Gao
157e72e831 drm/amdgpu: add sdma ip block for sienna_cichlid (v5) 
Sienna_Cichlid have 4 sdma controllers.

v2: add missing license to sdma_common.h (Alex)
v3: rebase (Alex)
v4: squash in policy fix (Alex)
v4: squash in fw_name fix

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:52:04 -04:00