Huang Rui
a201b6ac20
drm/amd/powerplay: make athub pg bit configured by pg_flags
...
The athub pg features enabling should be indicated by pg_flags.
Reported-by: Lijo Lazar <Lijo.Lazar@amd.com >
Signed-off-by: Huang Rui <ray.huang@amd.com >
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-06-25 13:54:32 -05:00
Huang Rui
c12d410ff2
drm/amd/powerplay: make mmhub pg bit configured by pg_flags
...
The mmhub pg features enabling should be indicated by pg_flags.
Reported-by: Lijo Lazar <Lijo.Lazar@amd.com >
Signed-off-by: Huang Rui <ray.huang@amd.com >
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-06-25 13:54:32 -05:00
Harry Wentland
b4f199c7b0
drm/amdgpu: Enable DC support for Navi10
...
Enable the IP for navi10.
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-06-22 09:34:07 -05:00
Leo Liu
157710ea4d
drm/amdgpu: enable VCN2.0 DPG mode
...
It will be the default for VCN2.x family
Signed-off-by: Leo Liu <leo.liu@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Reviewed-by: James Zhu <James.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-06-21 18:59:32 -05:00
Tao Zhou
462a70d87e
drm/amdgpu: correct reference clock value on navi10
...
remove the divisor 4
Signed-off-by: Tao Zhou <tao.zhou1@amd.com >
Acked-by: Jack Xiao <Jack.Xiao@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-06-21 18:59:31 -05:00
Jack Xiao
6ff687319f
drm/amdgpu/nv: set vcn pg flag
...
Enable VCN power gating by default.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com >
Reviewed-by: Huang Rui <ray.huang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-06-21 18:59:27 -05:00
Tianci Yin
36f87f0acd
drm/amdgpu: disable some gfx light sleep
...
temporarily disable to avoid s3 test failure.
s3 test failure log:
"[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout,
signaled seq=8278, emitted seq=8281"
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com >
Signed-off-by: Tianci Yin <tianci.yin@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-06-21 18:59:27 -05:00
Hawking Zhang
c6b6a42175
drm/amdgpu: add navi10 common ip block (v3)
...
This adds the core SOC code for navi asics.
v1: add place holder and initial basic function (Ray)
v2: add new introduced functions to avoid reference
NULL pointer (Hawking)
v3L squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com >
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-06-21 18:59:23 -05:00
