Marc Zyngier
cc2d3216f5
irqchip: GICv3: ITS command queue
...
The ITS is configured through a number commands that the driver
issues to the HW using a memory-based circular buffer.
This patch implements the subset of commands that are required
for Linux.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com >
Link: https://lkml.kernel.org/r/1416839720-18400-5-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net >
2014-11-26 15:55:12 +00:00
Marc Zyngier
f5c1434c21
irqchip: GICv3: rework redistributor structure
...
The basic GICv3 driver has almost no use for the redistributor
(other than the basic per-CPU interrupts), but the ITS needs
a lot more from them.
As such, rework the set of data structures. The behaviour of the
GICv3 driver is otherwise unaffected.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com >
Link: https://lkml.kernel.org/r/1416839720-18400-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net >
2014-11-26 15:55:12 +00:00
Catalin Marinas
72c5839515
arm64: gicv3: Allow GICv3 compilation with older binutils
...
GICv3 introduces new system registers accessible with the full msr/mrs
syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent
binutils understand the new syntax. This patch introduces msr_s/mrs_s
assembly macros which generate the equivalent instructions above and
converts the existing GICv3 code (both drivers/irqchip/ and
arch/arm64/kernel/).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com >
Reported-by: Olof Johansson <olof@lixom.net >
Tested-by: Olof Johansson <olof@lixom.net >
Suggested-by: Mark Rutland <mark.rutland@arm.com >
Acked-by: Mark Rutland <mark.rutland@arm.com >
Acked-by: Jason Cooper <jason@lakedaemon.net >
Cc: Will Deacon <will.deacon@arm.com >
Cc: Marc Zyngier <marc.zyngier@arm.com >
2014-07-25 13:12:15 +01:00
Marc Zyngier
021f653791
irqchip: gic-v3: Initial support for GICv3
...
The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System register for the CPU interfaces (SRE)
- Support for more that 8 CPUs
- Locality-specific Peripheral Interrupts (LPIs)
- Interrupt Translation Services (ITS)
This patch adds preliminary support for GICv3 with ARE and SRE,
non-secure mode only. It relies on higher exception levels to grant ARE
and SRE access.
Support for LPI and ITS will be added at a later time.
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Reviewed-by: Zi Shen Lim <zlim@broadcom.com >
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org >
Reviewed-by: Tirumalesh Chalamarla <tchalamarla@cavium.com >
Reviewed-by: Yun Wu <wuyun.wu@huawei.com >
Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com >
Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com >
Tested-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com >
Acked-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com >
Acked-by: Catalin Marinas <catalin.marinas@arm.com >
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com >
Reviewed-by: Mark Rutland <mark.rutland@arm.com >
Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net >
2014-07-08 22:11:47 +00:00
