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18554 Commits

Author SHA1 Message Date
Christina Quast
891ffb8fcd ARM: dts: am335x: pepper: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:25 -07:00
Christina Quast
898c4a59bc ARM: dts: am335x: pdu001: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:24 -07:00
Christina Quast
781288d2bd ARM: dts: am335x: pcm-953: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:23 -07:00
Christina Quast
558fee9ab5 ARM: dts: am335x: osd335x-common: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:23 -07:00
Christina Quast
443fca762b ARM: dts: am335x: osd3358-sm-red: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:22 -07:00
Christina Quast
affcce6f7c ARM: dts: am335x: nano: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:22 -07:00
Christina Quast
c68a4ffd3d ARM: dts: am335x: moxa-uc-8100-me-t: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:21 -07:00
Christina Quast
4a424b0b16 ARM: dts: am335x: moxa-uc-2101: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:20 -07:00
Christina Quast
876144dd53 ARM: dts: am335x: moxa-uc-2100-common: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:20 -07:00
Christina Quast
c422b10e88 ARM: dts: am335x: lxm: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:19 -07:00
Christina Quast
387fbf73eb ARM: dts: am335x: igep0033: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-15 08:26:19 -07:00
Andreas Kemnade
8558c6e21c ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board 
The Banana Pi M2 Zero board has an AP6212 BT+Wifi combo chip
with Broadcom internals attached to UART1 and some gpios.
This addition is in line with similar boards.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
 2019-04-15 11:00:19 +02:00
Pablo Greco
635e1e78a6 ARM: dts: sun8i: v40: bananapi-m2-berry: Sort device node dereferences. 
The device node dereferences are out of order, sort them.

Signed-off-by: Pablo Greco <pgreco@centosproject.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
 2019-04-15 09:51:30 +02:00
Douglas Anderson
356150e86d ARM: dts: rockchip: vdd_gpu off in suspend for rk3288-veyron 
At some point long long ago the downstream GPU driver would crash if
we turned the GPU off during suspend.  For some context you can see:

https://chromium-review.googlesource.com/#/c/215780/5..6/arch/arm/boot/dts/rk3288-pinky-rev2.dts

At some point in time not too long after that got fixed.

It's unclear why the GPU is left enabled during suspend on the
mainline kernel.  Everything seems fine if I turn this off, so let's
do it.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2019-04-12 22:28:38 +02:00
Douglas Anderson
ed27ae71bf ARM: dts: rockchip: vcc33_ccd off in suspend for rk3288-veyron-chromebook 
As per my comments when the device tree for rk3288-veyron-chromebook
first landed:

> Technically I think vcc33_ccd can be off since we have
> 'needs-reset-on-resume' down in the EHCI port (this regulator is for
> the USB webcam that's connected to the EHCI port).
>
>  ...but leaving it on for now seems fine until we get suspend/resume
> more solid.

It's probably about time to do it right.

[1] https://lore.kernel.org/linux-arm-kernel/CAD=FV=U37Yx8Mqk75_x05zxonvdc3qRMhqp8TyTDPWGHqSuRqg@mail.gmail.com/

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2019-04-12 22:28:21 +02:00
Roger Quadros
bcbb63b802 ARM: dts: dra7: Separate AM57 dtsi files 
AM5 and DRA7 SoC families have different set of modules
in them so the SoC sepecific dtsi files need to be separated.

e.g. Some of the major differences between AM576 and DRA76

		DRA76x	AM576x

USB3		x
USB4		x
ATL		x
VCP		x
MLB		x
ISS		x
PRU-ICSS1		x
PRU-ICSS2		x

This patch only deals with disabling USB3, USB4 and ATL for
AM57 variants.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 09:57:07 -07:00
Christina Quast
33ef1394a9 ARM: dts: am335x: icev2: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:14 -07:00
Christina Quast
1f757e0616 ARM: dts: am335x: evmsk: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:13 -07:00
Christina Quast
ef2791fd13 ARM: dts: am335x: evm: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:12 -07:00
Christina Quast
6c4f9ebf86 ARM: dts: am335x: cm-t335: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:12 -07:00
Christina Quast
125a6f3c58 ARM: dts: am335x: chilisom: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:11 -07:00
Christina Quast
4e5835effc ARM: dts: am335x: chiliboard: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:11 -07:00
Christina Quast
e52a7204cd ARM: dts: am335x: bonegreen-common: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:10 -07:00
Christina Quast
9faf08c2e6 ARM: dts: am335x: boneblue: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:10 -07:00
Christina Quast
ada077fa90 ARM: dts: am335x: bonegreen-wireless: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:09 -07:00
Christina Quast
0b119fafc8 ARM: dts: am335x: base0033: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:09 -07:00
Christina Quast
11ce1e0897 ARM: dts: am335x: baltos: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:08 -07:00
Christina Quast
8ce8c4b31a ARM: dts: am335x: baltos-leds: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:07 -07:00
Christina Quast
f6385bd149 ARM: dts: am335x: baltos-ir5221: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:07 -07:00
Christina Quast
a48d48e653 ARM: dts: am335x: baltos-ir3220: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:06 -07:00
Christina Quast
7229d544c8 ARM: dts: am335x: baltos-ir2110: Replaced register offsets with defines 
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2019-04-12 08:55:06 -07:00
Biju Das
0725a5478e ARM: dts: iwg23s-sbc: Enable HS-USB 
Enable HS-USB device for the iWave SBC based on RZ/G1C.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:26:09 +02:00
Biju Das
307ca5cf47 ARM: dts: r8a77470: Add HSUSB device nodes 
Define the r8a77470 generic part of the HSUSB0/1 device nodes.

Currently the renesas_usbhs driver doesn't handle multiple phys and we
don't have a proper hardware to validate such driver changes.

So for hsusb1 it is assumed that usbphy0 will be enabled by either
channel0 host or device.

In future, if any boards support hsusb1, we will need to add multiple phy
support in the renesas_usbhs driver and override the board dts to enable
the same.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:24:35 +02:00
Biju Das
034484c4a3 ARM: dts: iwg23s-sbc: Enable USB USB2.0 Host 
Enable USB2.0 host on the iwg23s sbc.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:23:15 +02:00
Biju Das
ce5940798c ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) device 
Define the r8a77470 generic part of the USB2.0 Host Controller device
nodes (ehci[01]/ohci[01]).

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:21:55 +02:00
Biju Das
e18cfb6e04 ARM: dts: iwg23s-sbc: Enable USB Phy[01] 
Enable USB phy[01] on iWave iwg23s sbc based on RZ/G1C SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:19:35 +02:00
Biju Das
1a675db440 ARM: dts: r8a77470: Add USB PHY DT support 
Define the r8a77470 generic part of the USB PHY device node.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:17:42 +02:00
Cao Van Dong
1631b58c7e ARM: dts: r8a77470: Add VIN support 
Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:06:25 +02:00
Cao Van Dong
3d59e55ef8 ARM: dts: r8a77470: Add PWM support 
Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the
RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 13:59:09 +02:00
Cao Van Dong
f408170d18 ARM: dts: r8a77470: Add HSCIF support 
Add hscif{0|1|2} nodes to dtsi for HSCIF support on the
RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 13:53:07 +02:00
Douglas Anderson
8a5deb4e31 ARM: dts: rockchip: Add DDR retention/poweroff to rk3288-veyron hogs 
Even though upstream Linux doesn't yet go into deep enough suspend to
get DDR into self refresh, there is no harm in setting these pins up.
They'll only actually do something if we go into a deeper suspend but
leaving them configed always is fine.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2019-04-12 13:14:29 +02:00
Matthias Kaehlcke
ac60c5e33d ARM: dts: rockchip: Add dynamic-power-coefficient for rk3288 
The value was determined with the following method:

- take CPUs 1-3 offline
- for each OPP
  - set cpufreq min and max freq to OPP freq
  - start dhrystone benchmark
  - measure CPU power consumption during 10s
  - calculate Cx for OPPx
    - Cx = (Px - P1) / (Vx²fx - V1²f1)          [1]
      using the following units: mW / Ghz / V   [2]
- C = avg(C2, ..., Cn)

[1] see commit 4daa001a17 ("arm64: dts: juno: Add cpu
     dynamic-power-coefficient information")
[2] https://patchwork.kernel.org/patch/10493615/#22158551

FTR, these are the values for the different OPPs:

freq (kHz)   	mV		Px (mW)		Cx

126000		900		39
216000		900		66		370
312000		900		95		372
408000		900		122		363
600000		900		177		359
696000		950		230		363
816000		1000		297		361
1008000		1050		404		362
1200000		1100		528		362
1416000		1200		770		377
1512000		1300		984		385
1608000		1350		1156		394

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2019-04-12 12:06:09 +02:00
Heiko Stuebner
07f08d9cee ARM: dts: rockchip: bulk convert gpios to their constant counterparts 
Rockchip SoCs use 2 different numbering schemes. Where the gpio-
controllers just count 0-31 for their 32 gpios, the underlying
iomux controller splits these into 4 separate entities A-D.

Device-schematics always use these iomux-values to identify pins,
so to make mapping schematics to devicetree easier Andy Yan introduced
named constants for the pins but so far we only used them on new
additions.

Using a sed-script created by Emil Renner Berthing bulk-convert
the remaining raw gpio numbers into their descriptive counterparts
and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
mappings:

/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/<RK_GPIO\([0-9]\) /<\1 /g
s/<\([^ ][^ ]*  *\)0 /<\1RK_PA0 /g
s/<\([^ ][^ ]*  *\)1 /<\1RK_PA1 /g
s/<\([^ ][^ ]*  *\)2 /<\1RK_PA2 /g
s/<\([^ ][^ ]*  *\)3 /<\1RK_PA3 /g
s/<\([^ ][^ ]*  *\)4 /<\1RK_PA4 /g
s/<\([^ ][^ ]*  *\)5 /<\1RK_PA5 /g
s/<\([^ ][^ ]*  *\)6 /<\1RK_PA6 /g
s/<\([^ ][^ ]*  *\)7 /<\1RK_PA7 /g
s/<\([^ ][^ ]*  *\)8 /<\1RK_PB0 /g
s/<\([^ ][^ ]*  *\)9 /<\1RK_PB1 /g
s/<\([^ ][^ ]*  *\)10 /<\1RK_PB2 /g
s/<\([^ ][^ ]*  *\)11 /<\1RK_PB3 /g
s/<\([^ ][^ ]*  *\)12 /<\1RK_PB4 /g
s/<\([^ ][^ ]*  *\)13 /<\1RK_PB5 /g
s/<\([^ ][^ ]*  *\)14 /<\1RK_PB6 /g
s/<\([^ ][^ ]*  *\)15 /<\1RK_PB7 /g
s/<\([^ ][^ ]*  *\)16 /<\1RK_PC0 /g
s/<\([^ ][^ ]*  *\)17 /<\1RK_PC1 /g
s/<\([^ ][^ ]*  *\)18 /<\1RK_PC2 /g
s/<\([^ ][^ ]*  *\)19 /<\1RK_PC3 /g
s/<\([^ ][^ ]*  *\)20 /<\1RK_PC4 /g
s/<\([^ ][^ ]*  *\)21 /<\1RK_PC5 /g
s/<\([^ ][^ ]*  *\)22 /<\1RK_PC6 /g
s/<\([^ ][^ ]*  *\)23 /<\1RK_PC7 /g
s/<\([^ ][^ ]*  *\)24 /<\1RK_PD0 /g
s/<\([^ ][^ ]*  *\)25 /<\1RK_PD1 /g
s/<\([^ ][^ ]*  *\)26 /<\1RK_PD2 /g
s/<\([^ ][^ ]*  *\)27 /<\1RK_PD3 /g
s/<\([^ ][^ ]*  *\)28 /<\1RK_PD4 /g
s/<\([^ ][^ ]*  *\)29 /<\1RK_PD5 /g
s/<\([^ ][^ ]*  *\)30 /<\1RK_PD6 /g
s/<\([^ ][^ ]*  *\)31 /<\1RK_PD7 /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)0 /<\1RK_FUNC_GPIO /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)RK_FUNC_\([1-9]\) /<\1\2 /g

Suggested-by: Emil Renner Berthing <esmil@mailme.dk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2019-04-11 14:38:26 +02:00
Matthias Kaehlcke
280fa34975 ARM: dts: rockchip: Add BT_EN to the power sequence for veyron 
Add GPIO D5 (BT_ENABLE_L) as reset-GPIO to the power sequence for the
Bluetooth/WiFi module. On devices with a Broadcom module the signal
needs to be asserted to use Bluetooth.

Note that BT_ENABLE_L is a misnomer in the schematics, the signal
actually is active-high.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2019-04-11 13:37:47 +02:00
Matthias Kaehlcke
2f60eb2f03 ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron 
Some veyron devices have a Bluetooth controller connected on UART0.
The UART needs to operate at a high speed, however setting the clock
rate at initialization has no practical effect. During initialization
user space adjusts the UART baudrate multiple times, which ends up
changing the SCLK rate. After a successful initiatalization the clk
is running at the desired speed (48MHz).

Remove the unnecessary clock rate configuration from the DT.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2019-04-11 13:35:55 +02:00
Yannick Fertré
3fca6a1ab9 ARM: dts: stm32: enable cec on stm32mp157a-dk1 board 
Enable CEC (Consumer Electronics Control) device.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
 2019-04-11 11:22:07 +02:00
Yannick Fertré
5eaae04941 ARM: dts: stm32: add cec pins muxing on stm32mp157 
Add a new pin muxing for cec.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
 2019-04-11 11:22:07 +02:00
Yannick Fertré
63834ff2d6 ARM: dts: stm32: add ltdc pins muxing on stm32mp157 
Add ltdc pins muxing on stm32mp157.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
 2019-04-11 11:22:06 +02:00
Yannick Fertré
f85c8acc7a ARM: dts: stm32: add I2C sleep pins muxing on stm32mp157 
Add I2C sleep pins muxing for low power mode.

Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
 2019-04-11 11:22:06 +02:00
Yannick Fertré
81987fff52 ARM: dts: stm32: add power supply of otm8009a on stm32mp157c-dk2 
This patch adds a new property (power-supply) to panel otm8009a (orisetech)
on stm32mp157c-dk2  & regulator v3v3.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
 2019-04-11 11:22:06 +02:00