2 Commits

Author	SHA1	Message	Date
Yash Shah	5545b6d1ba	RISC-V: Add DT documentation for SiFive L2 Cache Controller ... Add device tree bindings for SiFive FU540 L2 cache controller driver Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	2019-05-16 20:42:13 -07:00
Palmer Dabbelt	8caea50236	dt-bindings: RISC-V CPU Bindings ... This patch adds device tree bindings for RISC-V CPUs, patterned after the ARM device tree CPU bindings. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>	2017-09-25 15:50:57 -07:00