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11865 Commits

Author SHA1 Message Date
Huang Rui
013fd3a61a drm/amd/powerplay: don't include the smu11 driver if header in smu v11 (v2) 
This header is actually for each asic, so we should not include in smu_v11_0.c.
And rename the one for navi10.

v2: add hack for XGMI (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
6a36e3e57c drm/amd/powerplay: move getting MAX_FAN_RPM value to asic level 
Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to
asic level.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
8890fe5f43 drm/amd/powerplay: introduce smu power source type to handle AC/DC source for each asic 
This patch introduces new smu power source type, it's to handle the different
AC/DC source defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
973849042e drm/amd/powerplay: move Watermarks_t uses into asic level 
This patch moves the rest of Watermarks_t uses into asic level. It's to avoid
the conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
8b1f4c87a3 drm/amd/powerplay: move SmuMetrics_t uses into asic level 
This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the
conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
ee0db82027 drm/amd/powerplay: move PPTable_t uses into asic level 
This patch moves the rest of PPTable_t uses into asic level. It's to avoid the
conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
cbfba01dde drm/amd/powerplay: use the table size member in the structure instead of getting directly 
This patch uses the table size member in the structure instead of getting
directly, because the table is different in each asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
33bd73ae6c drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx as the input 
Table id may be different for each asic, so it's good to use this as the input
for common interface.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Alex Deucher
8b2ae145de drm/amd/powerplay/smu11: remove smu_update_table_with_arg 
Nothing was using it.  Just replace with smu_update_table
which is what everything was using via a wrapper anyway.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
22c9c6ca96 drm/amd/powerplay: add tables_init interface for each asic 
The smc tables defines should be in the asic level.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
cdb0c632e4 drm/amd/powerplay: init table_count for smu tables on asic level 
TABLE_COUNT should be inited in asic level. Because the value may be different
on each asic even on the same ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
2436911bdb drm/amd/powerplay: introduce smu table id type to handle the smu table for each asic 
This patch introduces new smu table type, it's to handle the different smu table
defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
ffcb08dfaa drm/amd/powerplay: introduce smu feature type to handle feature mask for each asic 
This patch introduces new smu feature type, it's to handle the different feature
mask defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Huang Rui
0de94acf90 drm/amd/powerplay: introduce smu clk type to handle ppclk for each asic 
This patch introduces new smu clk type, it's to handle the different ppclk
defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:26 -05:00
Hawking Zhang
54b998ca8d drm/amdgpu: enable sw smu driver for navi10 by default 
Navi10 will use sw smu driver for dynamic power managment,
while vega20 could also use sw smu driver when amdgpu_dpm is
set to 2

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
a899848805 drm/amd/powerplay: enable DCEFCLK dpm support 
Enabale DCEFCLK dpm on navi10

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
acbcc111ce drm/amd/powerplay: gfxoff-seperate the Vega20 case 
seperate the Vega20 case from navi10 for gfxoff so that gfxoff
won't be allowed on Vega20

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
9e04021602 drm/amd/amdgpu: fw version check with gfxoff 
1. check the firmware version when enabling gfxoff
2. overwrite the pptable to make sure gfxoff is really
enabled on navi10

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
bca325280d drm/amd: add gfxoff support on navi10 
add the gfxoff interface to navi10,it's disabled by default.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
77ee9caf38 drm/amd/powerplay: add allowed feature mask for navi10 
add smu feature mask:
1.FEATURE_DPM_PREFETCHER_BIT
2.FEATURE_DPM_PREFETCHER_BIT
3.FEATURE_ATHUB_PG

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
74c958a376 drm/amd/powerplay: optimization feature mask function for asic 
1.change function return value type: from "unallowed" to "allowed"
2.replace feature mask number with feature macro, the code will clear.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
5586348236 drm/amd/powerplay: remove duplicate code from smu hw init 
remove duplicate code (un-used) in smu

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
b55c83a743 drm/amd/powerplay: implement smc firmware v2.1 for smu11 
1.add smc_firmware_header_v2_1 hfirmware support, support more pptable in smc firmware.
2.optimization current pptable load framework.
3.rename read_pptable_from_vbios with setup_pptable.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
19d894b92d drm/amd/powerplay: add smu11 smu_if_version check for navi10 
add smu11 fw version check for navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
e17980535b drm/amd/powerplay: move the function of is_dpm_running to asic file 
the function os is_dpm_running is aisc related function,
so move them to asic file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
6d22f1aa92 drm/amd/powerplay: move the function of read_sensor to asic file 
The read_sensor functions has asic related parts code,
so move them to asic file to implement.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
86eb3ed3d3 drm/amd/powerplay: move the function of uvd&vce dpm to asic file 
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
667273c166 drm/amd/powerplay: move the function of get[set]_power_profile to asic file 
The callback of get[set]_power_profile is asic related function,
so move theme into vega20_ppt file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kevin Wang
940680c3b4 drm/amd/powerplay: move the funciton of conv_profile_to_workload to asic file 
the function of conv_profile_to_workload is asic related function,
so move them into vega20_ppt file

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Kenneth Feng
1e87e0124b drm/amd/powerplay: enable power features 
the below smu related power features can be enabled now.
1.Prefetcher
2.GFX DPM
3.SOCCLK DPM
4.MP0CLK DPM
5.LCLK DPM
6.GFX ULV
7.CG
8.PPT
9.TDC
10.GFX EDC
11.VR0HOT
12.Fan Control
13.Thermal Control
14.LED Display
15.MMHub PG
16.ATHub PG

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Huang Rui
5ba80a0a81 drm/amd/powerplay: skip od feature on navi10 for the moment 
OD feature isn't enabled on navi10 so skip it for the moment.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:25 -05:00
Huang Rui
3a4dc27b43 drm/amd/powerplay: modify the feature mask to enable gfx/soc dpm 
So far, the gfx/soc dpm is enabled with feature mask set.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
879af1c65a drm/amd/powerplay: introduce the function to load the soft pptable for navi10 (v2) 
Driver is able to load soft pptable from smc bin file with this function. We
stored the soft pptable in the bottom of smc.bin that the version is v2.

v2: remove is_fw_v2_0 flag.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
0186eb9630 drm/amd/powerplay: smu needs to be initialized after rlc in direct mode 
For gfx 10, rlc firmware loading relies on smu firmware is loaded firstly, so in
direct type, it has to load smc ucode here before rlc. And meanwhile, the smu
initialization has to move after rlc, otherwise, smu message will get failure
during the handshake with rlc and smu.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
c16d001bf2 drm/amdgpu: fix the issue of checking on message mapping 
The navi10_message_map[index] scope should be in PPSMC_Message_Count not in
SMU_MSG_MAX_COUNT.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
336a1c825e drm/amdgpu: bump smc firmware header version to v2 (v2) 
This patch bumps smc firmware header version to v2 for storing soft pptable.

v2: fix the typo, and add prints for v2 header

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
9e8a163d9b drm/amd/powerplay: update smu11 driver if header for navi10 (v2) 
This patch updates smu11 driver if header for navi10 to match 42.09.00 smu
firmware.

v2: clean up comments

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Kenneth Feng
827440a901 drm/amd/powerplay: enable backdoor smu fw loading (v2) 
enable backdoor smu fw loading on navi10

v2: squash in define fix (Alex)

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
4009b9b589 drm/amd/powerplay: move bootup value before read pptable from vbios 
In navi10, we need read the pp_table_id from bootup value, then decide whether
use load the soft pptable.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
3152865035 drm/amd/powerplay: add navi10 smc ucode init and navi10 ppt functions setting 
This patch adds navi10 smc ucode init and ppt functions setting.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
2573e87074 drm/amd/powerplay: set smu v11 funcs for navi10 
Naiv10 also uses smu v11 functions.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
b3490673f9 drm/amd/powerplay: introduce the navi10 pptable implementation 
This patch introduces the navi10 pptable implementation, so far it is already
has firmware loading, pptable side loading, writing back to smc, and feature
mask enabling.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
980e04ec37 drm/amd/powerplay: fix the mp/smuio header for navi10 
SMU11 should use mp11 and smuio11 headers.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
55f72087af drm/amd/powerplay: update smu 11 driver if header for navi10 
This patch updates smu 11 driver if header for navi10.

UVD/VCE won't be used for navi10. Here, reverve them for vega20.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
dded62c71e drm/amd/powerplay: update smu v11 ppsmc header 
This patch updates smu v11 ppsmc header for navi10.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Huang Rui
0a5b8c7b94 drm/amdgpu: add to set navi ip blocks 
Set the IPs for navi10 in early_init like other asics.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Alex Deucher
bd1c0fdfc1 drm/amdgpu: add Navi10 pci ids 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Philip Cox
14328aa58c drm/amdkfd: Add navi10 support to amdkfd. (v3) 
KFD (kernel fusion driver) is the kernel driver
for the compute backend for usermode compute
stack.

v2: squash in updates (Alex)
v3: squash in rebase fixes (Alex)

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Hawking Zhang
e0d076574e drm/amdgpu: update golden setting programming logic 
Since from soc15, make sure only AndMasked bit get changed
when applied or_mask

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:24 -05:00
Hawking Zhang
6bdadb2072 drm/amdgpu: Add navi10 kfd support for amdgpu (v3) 
KFD (Kernel Fusion Driver) is the compute backend driver
for AMD GPUs.

v2: squash in updates (Alex)
v3: fix warnings (Alex)

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:23 -05:00