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11865 Commits

Author SHA1 Message Date
Le Ma
7d19b15f70 drm/amdgpu: add VMC1 interrupt client id for Arcturus 
New IH client id for VMC1.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
e78705ec5a drm/amdgpu: dynamically initialize IP offset for Arcturus 
Add support for the IP offsets on Arcturus.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
113b47e780 drm/amdgpu: increase max number of ip base instances to 8 
For Arcturus, the number of IP base instances is 8.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
fa5d2e6f0a drm/amdgpu: add SDMA 2~7 ip block type 
Add IP block type.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
8024f1d5e1 drm/amdgpu: add SDMA 2~7 interrupt client id for Arcturus 
Add new client ids.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
51cce480fd drm/amdgpu: use new mmhub interfaces for Arcturus 
Arcturus has two MMHUBs.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
2cb2ea1e07 drm/amdgpu: add mmhub v9.4.1 block for Arcturus (v2) 
Arcturus as an updated mmhub block. mmhub is the
memory controller hub used for sdma and multimedia.

v2: squash in AGP BAR programming (Alex)

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
c8a6e2a317 drm/amdgpu: add one more mmhub instance for Arcturus (v2) 
v2: set mmhub num under CHIP_ARCTURUS switch case and add one more mmhub id_mgr

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
1daa2bfa17 drm/amdgpu: add new member in amdgpu_device for vmhub counts per asic chip 
It aims to replace AMDGPU_MAX_VMHUBS in for loop to initialize registers.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Le Ma
a2d15ed733 drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number 
The number of GFXHUB/MMHUB may be expanded in later ASICs.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Le Ma
3de2ff5d60 drm/amdgpu: add gmc basic support for Arcturus 
Add initial GMC support for Arcturus

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Le Ma
d6c3b24ea2 drm/amdgpu: add Arcturus asic type 
Add asic type for Arcturus.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Le Ma
f1cf876931 drm/amdgpu: add Arcturus ip_offset header (v3) 
Provides the absolute offsets of the IP register
blocks.

v2: update chip name in source code
v3: squash in MP offset updates (Alex)

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Leo Liu
c54a60db0d drm/amdgpu: add VCN2.5 headers 
VCN is the multi-media block.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Le Ma
4f727ecefe drm/amdgpu: add sdma 4.2.2 header files for Arcturus 
SDMA is the system DMA block.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Le Ma
0e96cf7f67 drm/amdgpu: add mmhub 9.4.1 header files for Acrturus 
mmhub is the GPU memory hub used by SDMA and VCN.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Alex Deucher
d1daf8502e drm/amdgpu: consolidate navi14 IP init 
It's the same as navi10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Alex Deucher
2665ec4171 drm/amdgpu: disable concurrent flushes on Navi14 
Same thing applies to navi14 as navi10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Jack Xiao
ba02636de5 drm/amdgpu: enable gfxoff code path for navi14 
Based on navi10 gfxoff logic, enable the related code
path for navi14.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Xiaojie Yuan
0377b08823 drm/amdgpu/vcn: enable indirect DPG SRAM mode for navi14 
Enable VCN dynamic powergating for navi14.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Xiaojie Yuan
e017bb8035 drm/amd/powerplay: disable gfxoff for navi14 
gfxoff doesn't work on navi14 yet, so disable it for now

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Xiaojie Yuan
03917df7e5 drm/amdgpu/nv: set vcn pg flag for navi14 
Enable VCN power gating by default.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
c5cc14e34d drm/amd/display: disable display writeback for navi14 
not used.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
5e0f378d8a drm/amdgpu: enable async gfx ring for navi14 
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
d0c39f8cbf drm/amdgpu: enable clock gatings for navi14 
Set appropriate CG flags for navi14.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
29e6fd7c86 drm/amdgpu/athub2: set clock gating for navi14 
same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
408c49de9b drm/amdgpu/mmhub2: set clock gating for navi14 
same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
8687b47e3a drm/amdgpu: declare asd firmware for navi14 
So the dependency gets properly tracked.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <snow.zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
James Zhu
e149a2f6ed drm/amdgpu: Enable VCN on navi14 
Add navi14 vcn firmware, and enable VCN on navi14.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
baebcf2e91 drm/amd/display: skip to load dmcu firmware for navi14 
not needed for navi14 at the moment.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
e470d287c3 drm/amdgpu: skip to load ta firmware for navi14 
Not relevant on navi14.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Bhawanpreet Lakha
c6e764b40a drm/amd/display: add ASICREV defines v2 
Add revs for navi10 and 14.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Bhawanpreet Lakha
8fceceb69e drm/amd/display: add dm block 
enable DC for navi14.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Bhawanpreet Lakha
2ebe177344 drm/amd/display: add NAVI14 in resource construct 
Change the pipes to 5 if the asic is nv14

This is a temp patch, there was some refactor in the dml part of the code.
which is not in this branch. for now this is good, we can implement this
properly once we have an updated branch.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Bhawanpreet Lakha
fce651e393 drm/amd/display: add nv14 cases to amdgpu_dm 
Mostly shared with navi10.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
ab5e51211c drm/amdgpu: enable sw smu ip for navi14 
same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
b02ff12689 drm/amdgpu/smu11: add support for navi14 
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
7840d8babe drm/amdgpu/psp: start rlc autoload after psp received rlcg for navi14 
Update for navi14.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
4adc0732fc drm/amdgpu: enable psp ip block for navi14 
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
82522b2d7f drm/amdgpu/psp: add psp support for navi14 (v3) 
Same as navi10.

v2: squash in logic fix (Colin Ian King)
v3: squash in logic simplification (Alex)

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
691f69b6a6 drm/amdgpu: enable virtual display for navi14 
Virtual display is a sw based kms interface for virtualization
and emulation.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
a29bfd1283 drm/amdgpu: add ip blocks for navi14 
Add the initial IP blocks for navi14

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
5e71e011ff drm/amdgpu/soc15: add support for navi14 
same as navi10

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Jack Xiao
b8cb98cd3e drm/amdgpu/gfx10: fix programming of SC_HIZ_TILE_FIFO_SIZE field 
max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE
field is programmed in units of two entries, but 6 bits is insufficient
to hold value 128/2 = 64, so set this field as 0 which is interpreted by
the hardware as maximum physical fifo size(128).

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Tao Zhou
3ddec51511 drm/amdgpu/gfx10: update gfx golden settings for navi14 
Updated settings from hw team.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
4904ede127 drm/amdgpu/gfx10: update gfx golden settings for navi14 
Add updated settings from hw team.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
be184b4ccc drm/amdgpu/gfx: update gc_v10_1_1 golden setting 
Updated settings for hw team.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
7417846725 drm/amdgpu/gfx10: add gfx v10_1_1 golden settings for navi14 
Add golden settings for navi14.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
58acab6629 drm/amdgpu/gfx: add definition of mmCGTT_GS_NGG_CLK_CTRL 
Needed for clockgating.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
d55c193dbd drm/amdgpu/gfx10: set tcp harvest for navi14 
Update settings for navi14.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00