ROHM BD70528 is an ultra low power PMIC with similar 32K clk as
bd718x7. Only difference (from clk perspective) is register address.
Add support for controlling BD70528 clk using bd718x7 driver.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Split the bd718x7.h to ROHM common and bd718x7 specific parts
so that we do not need to add same things in every new ROHM
PMIC header. Please note that this change requires changes also
in bd718x7 sub-device drivers for regulators and clk.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The watchdog pclk is controlled from the secure GRF but we still
want to mention it explicitly to not use arbitary parent clocks
in the devicetree wdt node, so add a SGRF_GATE for it.
Suggested-by: Leonidas P. Papadakos <papadakospan@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The function devm_regmap_init_mmio() wouldn't return NULL pointer for
now, so only need to ensure the return value is not an error code.
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
devm_ioremap_resources() automatically requests resources and devm_ wrappers
do better error handling and unmapping of the I/O region when needed,
that would make drivers more clean and simple.
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch over to the more modern style of registering parents and simplify
the code in the process.
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It turns out that this PLL is not used on Tegra210, so there's no need
to enable it via the init table. Remove the init table entry for this
PLL to avoid it getting enabled at boot time. If the bootloader enabled
it and forgot to turn it off, the common clock framework will now know
to disable it because it is unused.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a
configuration that makes sense, so warn about it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
There is no need to warn if the reference PLL is enabled with the
correct defaults. Only warn if the boot values don't match the defaults.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Full-speed and low-speed USB devices do not work with Tegra210
platforms because of incorrect PLLU/PLLU_OUT1 clock settings.
When full-speed device is connected:
[ 14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb
[ 14.196295] usb 1-3: device descriptor read/64, error -71
[ 14.436311] usb 1-3: device descriptor read/64, error -71
[ 14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb
[ 14.812335] usb 1-3: device descriptor read/64, error -71
[ 15.052316] usb 1-3: device descriptor read/64, error -71
[ 15.164799] usb usb1-port3: attempt power cycle
When low-speed device is connected:
[ 37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[ 38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[ 38.564977] usb usb1-port3: attempt power cycle
This commit fixes the issue by:
1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock
because PLLU_OUT1 is parent of XUSB_FS_SRC.
2. changing PLLU post-divider to /2 (DIVP=1) according to Technical
Reference Manual.
Fixes: e745f992cf ("clk: tegra: Rework pll_u")
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As 'clk-raspberrypi' depends on RPi's firmware interface, which might be
configured as a module, the cpu clock might not be available for the
cpufreq driver during it's init process. So we register the
'raspberrypi-cpufreq' platform device after the probe sequence succeeds.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Raspberry Pi's firmware offers an interface though which update it's
clock's frequencies. This is specially useful in order to change the CPU
clock (pllb_arm) which is 'owned' by the firmware and we're unable to
scale using the register interface provided by clk-bcm2835.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Raspberry Pi's firmware controls this pll, we should use the firmware
interface to access it.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
These functions are not called anywhere anymore, they can safely be
removed.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Low-Power Mode, when enabled, will make the "wait" MIPS instruction
suspend the system.
This is not really clock-related, but this bit happens to be in the
register set of the CGU.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The cgu.h has structures that contain 'clk_onecell_data' and 'clk_hw'
structures (no pointers), so the <linux/clk-provider.h> header should be
included.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
[sboyd@kernel.org: Drop removal of includes in drivers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This allows to easily determine the parent in shell scripts without
parsing more complex files.
Add the clk_parent file for all clks which can have a parent, not just
muxes. This way it can be used to determine the clk tree structure
without parsing more complex files.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
A boolean expression already evaluates to true or false, so there is no
need to check the result and return true or false explicitly.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The fixed dividers for the emac clocks should be 2 not 4.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The 98DX1135 is a switch chip with an integrated CPU. This is similar to
the 98DX4122 except that the core clock speed is fixed to 166Mhz.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add managed version of the clk_bulk_get_optional() helper function.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
[sboyd@kernel.org: Mark __devm_clk_bulk_get() static]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk_bulk_get_optional() allows to get a group of clocks where one
or more is optional. For a not available clock, e.g. not specifed
in the clock consumer node in DT, its respective struct clk pointer
will be NULL. This allows for operating on a group of returned
clocks (struct clk_bulk_data array) with existing clk_bulk* APIs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The possible parent printing function duplicates a bunch of if
conditions. Pull that into another function so we can print an extra
character at the end, either a space or a newline. This way we can add
the required newline that got lost here and also shorten the code.
Fixes: 2d156b78ce ("clk: Fix debugfs clk_possible_parents for clks without parent string names")
Cc: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Pull Allwinner sunxi-ng clk driver parent relation rewrite part 1 - take 2
from Chen-Yu Tsai:
"The first part of ongoing work to convert the sunxi-ng clk driver from
using global clock name strings to describe clk parenting, to having
direct struct clk_hw pointers, or local names based on clock-names from
the device tree binding.
This is based on Stephen Boyd's recent work allowing clk drivers to
specify clk parents using struct clk_hw * or parsing DT phandles in the
clk node.
This series can be split into a few major parts:
1) The first patch is a small fix for clk debugfs representation.
2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
situations I encountered, or assume I will encounter, such as single
internal (struct clk_hw *) parent, single DT (struct clk_parent_data
.fw_name), multiple internal parents, and multiple mixed (internal +
DT) parents. A special variant for just an internal single parent is
added, CLK_HW_INIT_HWS, which lets the driver share the singular
list, instead of having the compiler create a compound literal every
time. It might even make sense to only keep this variant.
3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
is the same as the single parent CLK_HW_INIT_* helpers.
4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
either struct clk_hw * or DT .fw_name types, whichever the hardware
requires.
5) The beginning of SUNXI_CCU_GATE conversion to local parent
references. This part is not done. They are included as justification
and examples for the shared list of clk parents case."
* tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (25 commits)
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: gate: Add macros for referencing local clock parents
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
clk: fixed-factor: Add CLK_FIXED_FACTOR_HWS which takes list of struct clk_hw *
...
Call imx_register_uart_clocks() API to keep uart clocks enabled
when earlyprintk or earlycon is active.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Some of i.MX SoCs' clock driver use platform driver model,
and they need to call imx_register_uart_clocks() API, so
imx_register_uart_clocks() API should NOT be in .init section.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_HWS
as the parent clock is internal to this clock unit.
To avoid duplication of clock definitions, we fix up the parent
reference for A83T in the A83T init function.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_DATA to
specify the parent clock.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw,
and .parent_data, for clk drivers to specify parents using a combination
of device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.
Add four new macros:
- SUNXI_CCU_GATE_HW, that can take a struct clk_hw pointer, instead
of a string, as its parent.
- SUNXI_CCU_GATE_FW that takes a string to match a clock-names entry
in the device tree to specify the clock parent.
- SUNXI_CCU_GATE_HWS that takes an array of struct clk_hw * as its
parent. This allows the array to be shared with other clk
declarations.
- SUNXI_CCU_GATE_DATA that takes an array of struct clk_parent_data *
as its parent. This allows the array to be shared with other clk
declarations.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
A forward declaration for struct clk_fixed_factor pll_periph0_4x_clk
is added as the definitions of the fixed factor clocks appear much later
in the file. The position of fixed factor clock definitions will be
moved for all drivers at a later time, before the conversion of all
other clock types.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Flexible array members should be denoted using [] instead of [0], else
gcc will not warn when they are no longer at the end of the structure.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Make cpg_mssr_priv.clks[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the driver-private
structure and array of available clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Make mstp_clock_group.clks[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the group-private
structure and array of module clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Make div6_clock.parents[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the clock-private
structure and array of parent clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
New fields were added, but kerneldoc was forgotten, or inserted at the
wrong place.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation http www opensource org
licenses gpl license html http www gnu org copyleft gpl html
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 3 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081201.897982733@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
