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6092 Commits

Author SHA1 Message Date
Andrey Grodzovsky
c43b849f89 drm/amdgpu: Use new mode2 reset interface for RV. 
Integrate the mode2 reset into rest sequence.

v2:
Check ppfuncs pointer for NULL

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 11:00:44 -05:00
Andrey Grodzovsky
b1f5b4538e dmr/amdgpu: Fix compile error with CONFIG_DRM_AMDGPU_GART_DEBUGFS 
Double defintion of 'i'

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:59:17 -05:00
Gang Ba
108b4d928c drm/amd/amdgpu: Update VM function pointer 
When VM state changed and system in large bar mode,
make sure to use CPU update function, otherwise use
SDMA function.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gang Ba <gaba@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:58:28 -05:00
Yong Zhao
8b7d6157f2 drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0 for GFX10 
We have done this for pre-GFX10 asics, but GFX10 did not pick up the
new change. The below is the commit message for that change.

This is recommended by HW designers. Previously when it was set to 1,
the PDE walk error in VM fault will be treated as
PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.

The above behavior is kind of abnormal. Furthermore, the
PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
and it never made it way to production. Therefore, we should set it to 0.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:58:14 -05:00
Yong Zhao
5d36d4c976 drm/amdgpu: Add more page fault info printing for GFX10 
The printing we did for GFX9 was not propogated to GFX10 somehow, so fix
it now.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:58:08 -05:00
Yong Zhao
4e0ae5e214 drm/amdgpu: Add printing for RW extracted from VM_L2_PROTECTION_FAULT_STATUS 
RW is also useful in most cases.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:58:02 -05:00
Oak Zeng
5413fce4b2 drm/amdkfd/gfx10: Calling amdgpu functions to invalidate TLB 
Calling amdgpu function to invalidate TLB, instead of using a
kfd implementation. Delete the kfd local TLB invalidation
implementation.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:57:55 -05:00
Oak Zeng
3ff985485b drm/amdgpu: Export function to flush TLB of specific vm hub 
This is for kfd to reuse amdgpu TLB invalidation function.
On gfx10, kfd only needs to flush TLB on gfx hub but not
on mm hub. So export a function for KFD flush TLB only on
specific hub.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:57:48 -05:00
Stephen Rothwell
2568cedc13 drm/amdgpu: MODULE_FIRMWARE requires linux/module.h 
Fixes: 6a7a0bdbfa ("drm/amdgpu: add psp_v12_0 for renoir (v2)")
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:52:01 -05:00
Tao Zhou
d6e0cbb152 drm/amdgpu: implement querying ras error count for mmhub 
get mmhub ea ras error count by accessing EDC_CNT register

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:51:50 -05:00
Kevin Wang
f0f50dcfd4 drm/amdgpu: use exiting amdgpu_ctx_total_num_entities function 
simplify driver code.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:51:45 -05:00
Kevin Wang
b81e57fbf9 drm/amdgpu: fix typo error amdgput -> amdgpu 
fix typo error:
change function name from "amdgput_ctx_total_num_entities" to
"amdgpu_ctx_total_num_entities".

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:51:37 -05:00
Christoph Hellwig
244511f386 drm/amdgpu: simplify and cleanup setting the dma mask 
Use dma_set_mask_and_coherent to set both masks in one go, and remove
the no longer required fallback, as the kernel now always accepts
larger than required DMA masks.  Fail the driver probe if we can't
set the DMA mask, as that means the system can only support a larger
mask.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:51:01 -05:00
Christoph Hellwig
90489ce18c drm/amdgpu: handle PCIe root ports with addressing limitations 
amdgpu uses a need_dma32 flag to indicate to the drm core that some
allocations need to be done using GFP_DMA32, but it only checks the
device addressing capabilities to make that decision.  Unfortunately
PCIe root ports that have limited addressing exist as well.  Use the
dma_addressing_limited instead to also take those into account.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-15 10:51:00 -05:00
Alex Deucher
b8cf3219cc drm/amdgpu: flag renoir as experimental for now 
The current code won't likely work on production hw when
it ships so leave it as experimental until it's ready.

Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:51 -05:00
Huang Rui
c9d0ca8528 drm/amdgpu: skip mec2 jump table loading for renoir 
Renoir need not load mec2 jump table with psp.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:51 -05:00
Huang Rui
444a0fea51 drm/amdgpu: use direct loading on renoir vcn for the moment 
PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use
direct loading for the moment till the issue is addressed.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
8deac23636 drm/amdgpu: set fw default loading by psp for renoir 
By default, set amdgpu ucode type to AMDGPU_FW_LOAD_PSP.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
40c8a3293b drm/amdgpu: update lbpw for renoir 
enable gfx_v9_0_init_lbpw for renoir

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
95f9e74c3a drm/amdgpu: enable power gating for renoir 
enable gfx power gating for renoir

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
f78e007f76 drm/amdgpu: enable clock gating for renoir 
enable gfx&common clock gating for renoir

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Leo Liu
279ba48e1f drm/amdgpu: add VCN2.0 to Renoir IP blocks 
Thus enable VCN2.0 for Renoir

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Leo Liu
0c6b391d68 drm/amdgpu: enable Doorbell support for Renoir (v2) 
Add VCN range aperture to NBIO 7.0

v2: rebase (Alex)

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Leo Liu
dc9b6e934b drm/amdgpu: enable Renoir VCN firmware loading 
By adding new Renoir VCN firmware

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
a46e1716f3 drm/amdgpu: add sdma golden settings for renoir 
This patch adds sdma golden settings for renoir asic.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
33294eb8cb drm/amdgpu: add gfx golden settings for renoir (v2) 
This patch adds gfx golden settings for renoir real asic.

v2: update settings (Alex)

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
6a7a0bdbfa drm/amdgpu: add psp_v12_0 for renoir (v2) 
1. Add psp ip block
2. Use direct loading type by default and it can also config psp
   loading type.
3. Bypass sos fw loading and xgmi&ras interface

v2: drop TA loading

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
6b3ad3b2da drm/amdgpu: set rlc funcs for renoir 
add gfx_v9_0_rlc_funcs for renoir

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
e09ce48182 drm/amdgpu: add asic funcs for renoir 
add asic funcs for renoir, init soc15_asic_funcs

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
b1326bbc63 drm/amdgpu: enable dce virtual ip module for Renoir 
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
0126abd4d1 drm/amdgpu: fix no interrupt issue for renoir emu 
In renoir's ih model, there's a change in mmIH_CHICKEN
register, that limits IH to use physical address directly.
Those chicken bits need to be programmed first.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
61bdb39c91 drm/amdgpu: add renoir pci id 
Add Renoir PCI id support.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
05e1f0e0ab drm/amdgpu: set ip blocks for renoir 
Enable ip blocks for renoir.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
2d49738ae1 drm/amdgpu: add sdma support for renoir 
Add renoir checks to appropriate places.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
1aafd447bc drm/amdgpu: add gfx support for renoir 
Add Renoir checks to gfx9 code.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
378d53898a drm/amdgpu: set fw load type for renoir 
This patch sets fw load type as direct for renoir for the moment.
Will switch to psp when psp is ready.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
8787ee0145 drm/amdgpu: add gmc v9 supports for renoir 
Add gfx memory controller support for renoir.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
080deab66d drm/amdgpu: add soc15 common ip block support for renoir 
This patch adds common ip support for renoir.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
b51a26a02a drm/amdgpu: add renoir support for gpu_info and ip block setting 
This patch adds renoir support for gpu_info firmware and ip block setting.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
1eee4228a5 drm/amdgpu: add renoir asic_type enum 
This patch adds renoir to amd_asic_type enum and amdgpu_asic_name[].

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Pierre-Eric Pelloux-Prayer
62cfcb9e23 drm/amdgpu: fix gfx9 soft recovery 
The SOC15_REG_OFFSET() macro wasn't used, making the soft recovery fail.

v2: use WREG32_SOC15 instead of WREG32 + SOC15_REG_OFFSET

Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Le Ma
a840159c82 drm/amdgpu: enable mmhub clock gating for Arcturus 
Init MC_MGCG/LS flag. Also apply to athub CG.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Le Ma
cb15e8046d drm/amdgpu: add mmhub clock gating for Arcturus 
Add 2 mmhub instances CG

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Le Ma
15e2f43a72 drm/amdgpu: increase CGCG gfx idle threshold for Arcturus 
Follow the hw spec, and no need to consider gfxoff on Arcturus

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Le Ma
f9da7c4384 drm/amdgpu: add GFX_CP_LS flag to Arcturus 
Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before
    drm/amdgpu: enable gfx clock gating for Arcturus

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Tao Zhou
5212a3bdf0 drm/amdgpu: remove ras block's feature status info in sysfs 
feature mask info is enough for rocm tool,
"cat /sys/class/drm/card0/device/ras/features" will get the
info like this:

feature mask: 0x3ffb

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
bee7b51ac9 drm/amdgpu: split athub clock gating from mmhub 
Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic
not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
f7ee199528 drm/amdgpu: enable sdma clock gating for Arcturus 
Init sdma MGCG/LS flag

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
8dc7e07cff drm/amdgpu: add sdma clock gating for Arcturus 
Add ARCTURUS case in sdma set clockgating function

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
78864760c2 drm/amdgpu: support sdma clock gating for more instances 
Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00