3 Commits

Author	SHA1	Message	Date
Chen-Yu Tsai	3de64bf187	clk: sunxi-ng: Support separately grouped PLL lock status register ... On the Allwinner A80 SoC, the PLL lock status indicators are grouped together in a separate register, as opposed to being scattered in each PLL's configuration register. Add a flag to support this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>	2017-01-30 08:36:20 +01:00
Maxime Ripard	7c09b85896	clk: sunxi-ng: Implement global pre-divider ... Some clocks have a global pre-divider that applies to all their parents. Since it might also apply to clocks that have a single parent, this is merged in the ccu_common structure, unlike the other pre-divider settings that are tied to a specific index, and thus a specific parent. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>	2017-01-23 11:45:02 +01:00
Maxime Ripard	1d80c14248	clk: sunxi-ng: Add common infrastructure ... Start our new clock infrastructure by adding the registration code, common structure and common code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com	2016-07-08 18:04:32 -07:00