Commit Graph

9510 Commits

Author SHA1 Message Date
Vijay Purushothaman
17dc92574b drm/i915: Fixup HDMI output on Valleyview
Fixed correct min, max vco limits and dip ctl reg

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-28 17:05:08 +02:00
Gajanan Bhat
19c03924d4 drm/i915: Add eDP support for Valleyview
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.

v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
interfaces
v4: removed unconditional enabling of 6bpc dithering based on comments
from Daniel & Jani Nikula. Also changed the display enabling order to
force eDP detection first.

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-28 17:04:38 +02:00
Vijay Purushothaman
2a8f64ca23 drm/i915: Enable DisplayPort in Valleyview
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.

Cleaned up DPLL calculations for Valleyview to support multi display
configurations.

v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: drop spurious whitespace changes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-28 17:02:08 +02:00
Vijay Purushothaman
74a4dd2e45 drm/i915: Program correct m n tu register for Valleyview
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-28 16:49:53 +02:00
Vijay Purushothaman
b56747aace drm/i915: Add Valleyview lane control definitions
Added DPIO data lane register definitions for Valleyview

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-28 16:48:27 +02:00
Vijay Purushothaman
ae33cdcfc6 drm/i915: Fix SDVO IER and status bits for Valleyview
Fixed SDVOB and SDVOC bit definitions for Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-28 16:46:55 +02:00
Vijay Purushothaman
9473c8f485 drm/i915: Set aux clk to 100MHz for Valleyview
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-28 16:42:52 +02:00
Alex Deucher
fb6ca6d154 drm/radeon: force MSIs on RS690 asics
There are so many quirks, lets just try and force
this for all RS690s.  See:
https://bugs.freedesktop.org/show_bug.cgi?id=37679

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2012-09-27 10:22:46 -04:00
Alex Deucher
3a6d59df80 drm/radeon: Add MSI quirk for gateway RS690
Fixes another system on:
https://bugs.freedesktop.org/show_bug.cgi?id=37679

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2012-09-27 10:22:45 -04:00
Marek Olšák
61051afd35 drm/radeon: allow MIP_ADDRESS=0 for MSAA textures on Evergreen
MIP_ADDRESS should point to the resolved FMASK for an MSAA texture.
Setting MIP_ADDRESS to 0 means the FMASK pointer is invalid (the GPU
won't read the memory then).

The userspace has to set MIP_ADDRESS to 0 and *not* emit any relocation
for it.

Signed-off-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2012-09-27 10:22:45 -04:00
Marek Olšák
46fc8781bf drm/radeon/kms: allow STRMOUT_BASE_UPDATE on RS780 and RS880
This is required to make streamout work there.

Signed-off-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2012-09-27 10:22:44 -04:00
Dmitry Cherkasov
fa87e62d35 drm/radeon: add 2-level VM pagetables support v9
PDE/PTE update code uses CP ring for memory writes.
All page table entries are preallocated for now in alloc_pt().

It is made as whole because it's hard to divide it to several patches
that compile and doesn't break anything being applied separately.

Tested on cayman card.

v2: rebased on top of "refactor set_page chipset interface v3",
    code cleanups

v3: switched offsets calc macros to inline funcs where possible,
    remove pd_addr from radeon_vm, switched RADEON_BLOCK_SIZE define,
    to 9 (and PTE_COUNT to 1 << BLOCK_SIZE)

v4 (ck): move "incr" documentation to previous patch, cleanup and
         document RADEON_VM_* constants, change commit message to
         our usual format, simplify patch allot by removing
         everything current not necessary, disable SI workaround.

v5: (agd5f): Fix typo in tables_size calculation in
             radeon_vm_alloc_pt().  Second line should have been
             '+=' rather than '='.

v6: fix npdes calculation. In scenario when pfns to be mapped overlap
two PDE spans:

   +-----------+-------------+
   | PDE span  | PDE span    |
   +-----------+----+--------+
          |         |
          +---------+
          | pfns    |
          +---------+

the following npdes calculation gives incorrect result:

npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 1;

For the case above picture it should give npdes = 2, but gives one.

This patch corrects it by rounding last pfn up to 512 border,
first - down to 512 border and then subtracting and dividing by 512.

v7: Make npde calculation clearer, fix ndw calculation.

v8: (agd5f): reserve enough for 2 full VM PTs, add some
             additional comments.

v9: fix typo in npde calculation

Signed-off-by: Dmitry Cherkasov <Dmitrii.Cherkasov@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:44 -04:00
Christian König
dce34bfd63 drm/radeon: refactor set_page chipset interface v5
Cleanup the interface in preparation for hierarchical page tables.

v2: add incr parameter to set_page for simple scattered PTs uptates
    added PDE-specific flags to r600_flags and radeon_drm.h
    removed superfluous value masking with 0xffffffff

v3: removed superfluous bo_va->valid checking
    changed R600_PTE_VALID to R600_ENTRY_VALID to handle PDE too

v4 (ck): fix indention style, rework and fix typos in commit message,
         add documentation for incr parameter, also use incr
         parameter for system pages

v5 (agd5f): use upper_32_bits() and minor white space fixes

Signed-off-by: Christian König <deathsimple@vodafone.de>
Signed-off-by: Dmitry Cherkassov <Dmitrii.Cherkasov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:43 -04:00
Michel Dänzer
af026c5bd1 drm/radeon: Fix scratch register leak in IB test.
Restructure the code to jump out via labels instead of directly returning
early. Also make error reporting consistent across all hardware generations.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Simon Kitching <skitching@vonos.net>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:42 -04:00
Alex Deucher
bced76f271 drm/radeon: restore backlight level on resume
Restore the backlight level on resume.  Some systems
need to explicitly restore the backlight level on
resume.

Fixes panel resume on my Trinity laptop and may fix the
following bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=43829
https://bugzilla.kernel.org/show_bug.cgi?id=46241

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:42 -04:00
Alex Deucher
6d92f81dcf drm/radeon: add get_backlight_level callback
Read back the backlight level from the hw.
Needed for proper backlight restoration on resume.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:41 -04:00
Alex Deucher
2e3b3b105a drm/radeon: only adjust default clocks on NI GPUs
SI asics store voltage information differently so we
don't have a way to deal with it properly yet.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2012-09-27 10:22:41 -04:00
Alex Deucher
c0fd0834aa drm/radeon: validate PPLL in crtc fixup
This allows us to bail if we can't support the requested
setup from a PPLL perspective.  Prevents broken setups
from being attempted.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:40 -04:00
Alex Deucher
57b35e29cf drm/radeon: work around KMS modeset limitations in PLL allocation (v2)
Since the current KMS API sets the mode independantly on
each crtc, we may end up with resource conflicts.  The PLL
allocation is one of those cases.  In the following example
we have 3 crtcs in use driving 2 DVI connectors and 1 DP
connector.  On the initial kernel modeset for fbdev, the
display topology ends up as follows:

crtc0 -> DP-0
crtc1 -> DVI-0
crtc2 -> DVI-1

Because this is the first modeset, all of the PLLs are
available as none have been assigned.  So we end up with
the following:

crtc0 uses DCPLL
crtc1 uses PPLL2
crtc2 uses PPLL1

When X starts, it assigns a different topology:

crtc0 -> DVI-0
crtc1 -> DP-0
crtc2 -> DVI-1

However, since the KMS API is per crtc, we set the mode on each
crtc independantly.  When it comes time to set the mode on crtc0,
the topology for crtc1 and crtc2 are still intact.  crtc1 and
crtc2 are already assigned PPLL2 and PPLL1 so when it comes time
to set the mode on crtc0, crtc1 and crtc2 have not been torn down
yet, so there appears to be no PLLs available.  In reality, we
are reconfiguring the entire display topology, however, since
each crtc is handled independantly, we don't know that in the
driver at each crtc mode set time.

This patch checks to see if the same connector is being driven by
another crtc, and if so, uses the PLL already associated with it.

v2: store connector in the radeon crtc struct, simplify checking.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:40 -04:00
Dave Airlie
d638163099 Merge branch 'drm-nouveau-fixes' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes
Another spurious dmesg quitening.

* 'drm-nouveau-fixes' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nvc0/fifo: ignore bits in PFIFO_INTR that aren't set in PFIFO_INTR_EN
2012-09-27 17:58:53 +10:00
Ben Widawsky
3bc2913e2c drm/i915: Fix set_caching locking
On the EINVAL case we don't release struct_mutex. It should be safe to
grab the lock after checking the parameters, which also resolves the
issues.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-27 08:45:11 +02:00
Jani Nikula
0c96c65b48 drm/i915: use adjusted_mode instead of mode for checking the 6bpc force flag
The dithering introduced in

commit 3b5c78a35c
Author: Adam Jackson <ajax@redhat.com>
Date:   Tue Dec 13 15:41:00 2011 -0800

    drm/i915/dp: Dither down to 6bpc if it makes the mode fit

stores the INTEL_MODE_DP_FORCE_6BPC flag in the private_flags of the
adjusted mode, while i9xx_crtc_mode_set() and ironlake_crtc_mode_set() use
the original mode, without the flag, so it would never have any
effect. However, the BPC was clamped by VBT settings, making things work by
coincidence, until that part was removed in

commit 4344b813f1
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Fri Aug 10 11:10:20 2012 +0200

Use adjusted_mode instead of mode when checking for
INTEL_MODE_DP_FORCE_6BPC to make the flag have effect.

v2: Don't forget to fix this in i9xx_crtc_mode_set() also, pointed out by
Daniel both before and after sending the first patch.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=47621
CC: Adam Jackson <ajax@redhat.com>
CC: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-27 08:42:10 +02:00
Ben Skeggs
833dd8224e drm/nvc0/fifo: ignore bits in PFIFO_INTR that aren't set in PFIFO_INTR_EN
PFIFO_INTR = 0x40000000 appears to be a normal case on nvc0/nve0 PFIFO,
the binary driver appears to completely ignore it in its PFIFO interrupt
handler and even masks off the bit (as we do) in PFIFO_INTR_EN at init
time.

The bits still light up in the hardware sometimes though, so lets just
ignore any bits we haven't explicitely requested.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-09-27 09:13:43 +10:00
Jesse Barnes
3bcedbe5f2 drm/i915: limit VLV IRQ enables to those we use
To match IVB.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-26 16:16:32 +02:00
Adam Jackson
da131a4626 drm/dp: Make sink count DP 1.2 aware
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-26 14:26:06 +02:00
Adam Jackson
07d3dc1839 drm/i915/dp: Be smarter about connection sense for branch devices
If there's no downstream device, DPCD success is good enough.  If
there's a hotplug-capable downstream device, count the number of
connected sinks in DP_SINK_STATUS and return success if it's non-zero.
Otherwise, probe DDC and report appropriately.

v2: Check DP_SINK_STATUS instead of something unrelated to sink status.

Tested-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-26 14:22:29 +02:00
Adam Jackson
b091cd928d drm/i915/dp: Fetch downstream port info if needed during DPCD fetch
v2: Fix parenthesis mismatch, spotted by Jani Nikula

Tested-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Fixup merge conflict and MAX_DOWNSTREAM #define as spotted by
Jani.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-26 14:21:29 +02:00
Adam Jackson
015b85a067 drm: Export drm_probe_ddc()
Tested-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-26 14:09:36 +02:00
Dave Airlie
3a75885848 drm/udl: limit modes to the sku pixel limits.
Otherwise when X starts we commonly get a black screen scanning
out nothing, its wierd dpms on/off from userspace brings it back,

With this on F18, multi-seat works again with my 1920x1200 monitor
which is above the sku limit for the device I have.

Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-09-26 18:40:21 +10:00
Dan Carpenter
68c4fce737 vmwgfx: corruption in vmw_event_fence_action_create()
We don't allocate enough data for this struct.  As soon as we start
modifying event->event on the next lines, then we're going beyond the
end of the memory we allocated.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@gmail.com>
2012-09-26 18:40:06 +10:00
Chris Wilson
f531dcb23f drm/i915: Wrap external callers to IPS state with appropriate locks
Finishes commit 02d719562e
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Aug 9 16:44:54 2012 +0200

    drm/i915: properly guard ilk ips state

The core functions were annotated with their locking requirements, but
we overlooked that they were exported, without any control over the
locking, to debugfs. So in order to enable debugfs to read the registers
without triggering sanity checks, we change the exported entry points to
properly take the required locks before calling the core routines.

Reported-by: yangguang <guang.a.yang@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55304
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-26 09:24:54 +02:00
Ben Widawsky
199adf40ae drm/i915: s/cacheing/caching/
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-26 09:24:36 +02:00
Paulo Zanoni
adf00b26d1 drm/i915: make sure we write all the DIP data bytes
... even if the actual infoframe is smaller than the maximum possible
size.

If we don't write all the 32 DIP data bytes the InfoFrame ECC may not
be correctly calculated in some cases (e.g., when changing the port),
and this will lead to black screens on HDMI monitors. The ECC value is
generated by the hardware.

I don't see how this should break anything since we're writing 0 and
that should be the correct value, so this patch should be safe.

Notice that on IVB and older we actually have 64 bytes available for
VIDEO_DIP_DATA, but only bytes 0-31 actually store infoframe data: the
others are either read-only ECC values or marked as "reserved". On HSW
we only have 32 bytes, and the ECC value is stored on its own separate
read-only register. See BSpec.

This patch fixes bug #46761, which is marked as a regression
introduced by commit 4e89ee174b:
    drm/i915: set the DIP port on ibx_write_infoframe

Before commit 4e89 we were just failing to send AVI infoframes when we
needed to change the port, which can lead to black screens in some
cases. After commit 4e89 we started sending infoframes, but with a
possibly wrong ECC value. After this patch I hope we start sending
correct infoframes.

Version 2:
  - Improve commit message
  - Try to make the code more clear

Cc: stable@vger.kernel.org
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=46761
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-26 09:24:09 +02:00
Ben Skeggs
79eee7aa0d drm/nvc0/ltcg: mask off intr 0x10
NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10
intrs we receive are normal and we can ignore them.

On Kepler NVIDIA *don't* do this, but the hardware appears to come up
with the bit masked off by default - so that's probably why :)

This should silence some interrupt spam seen on Fermi+ boards.

Backported patch from reworked nouveau kernel tree.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-09-26 12:43:10 +10:00
Ben Skeggs
c7ead11d0b drm/nouveau: silence a debug message triggered by newer userspace
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-09-26 12:41:19 +10:00
Paulo Zanoni
e2f12b070d drm/i915: remove unused variables from ironlake_crtc_mode_set
The last patches moved a lot of code from ironlake_crtc_mode_set to
sub-functions, so these variables became useless. You could get
warnings by enabling -Wunused-but-set-variable.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-25 10:44:06 +02:00
Paulo Zanoni
de13a2e3f8 drm/i915: extract compute_dpll from ironlake_crtc_mode_set
Too many lines just to compute the value of a single variable, so
move this to its own function.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-25 10:40:04 +02:00
Paulo Zanoni
f48d8f235a drm/i915: extract set_m_n from ironlake_crtc_mode_set
The set_m_n code was spread all over the mode_set function.

Version 2:
Don't set the DP M/N registers on ironlake_set_m_n. Daniel Vetter has
plans to add some encoder-specific callbacks. Also, on this version we
don't change the order we're writing the registers, making the code
change safer.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-25 10:37:34 +02:00
Paulo Zanoni
cc769b6257 drm/i915: don't recheck for invalid pipe bpp
As noticed by Daniel Vetter, intel_pipe_choose_bpp_dither should
already check for invalid bpp values and set a valid value, so remove
the recheck inside ironlake_crtc_mode_set and also replace a "default"
switch case inside ironlake_set_pipeconf with a BUG().

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-25 10:36:10 +02:00
Bjorn Helgaas
78c8f84302 Merge branch 'pci/yinghai-misc' into next 2012-09-24 17:24:11 -06:00
Yinghai Lu
84544a1dea PCI: Fix default vga ref_count
when __ARCH_HAS_VGA_DEFAULT_DEVICE is not defined, aka EFIFB is not used,
for static path, vga_default setting is through vga_arbiter_add_pci_device.
and later x86 pci_fixup_video, will skip setting again.
- subsys_initcall(vga_arb_device_init) come first to call
vga_arbiter_add_pci_device. It will call pci_get_dev to hold one reference.

for hotplug add path, even vga_arbiter_add_pci_device is called via
notifier, but it will check VGA_RSRC_LEGACY_MASK that is not set for
hotplug path.  So x86 pci_fixup_video will take over to call
vga_set_default_device().  It will not hold one refrence.

Later for hotplug remove path, vga_arbiter_del_pci_device that does not
check VGA_RSRC_LEGACY_MASK will call put_device and it will cause ref_count
to decrease extra. that will have that pci device get deleted early
wrongly.

Need to make get/put balance for both cases.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: x86@kernel.org
Cc: Dave Airlie <airlied@redhat.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Julia Lawall <julia@diku.dk>
Cc: Matthew Garrett <mjg@redhat.com>
2012-09-24 13:35:00 -06:00
Daniel Vetter
398b7a1b88 Merge tag 'v3.6-rc7' into drm-intel-next-queued
Manual backmerge of -rc7 to resolve a silent conflict leading to
compile failure in drivers/gpu/drm/i915/intel_hdmi.c.

This is due to the bugfix in -rc7:

commit b98b601672
Author: Wang Xingchao <xingchao.wang@intel.com>
Date:   Thu Sep 13 07:43:22 2012 +0800

    drm/i915: HDMI - Clear Audio Enable bit for Hot Plug

Since this code moved around a lot in -next git put that snippet at
the wrong spot. I've tried to fix this by making the conflict explicit
by merging a version for next with:

commit 3cce574f01
Author: Wang Xingchao <xingchao.wang@intel.com>
Date:   Thu Sep 13 11:19:00 2012 +0800

    drm/i915: HDMI - Clear Audio Enable bit for Hot Plug unconditionally

But that failed to solve the entire problem. To avoid pushing out
further -nightly branch to our QA where this is broken, do the
backmerge and manually add the stuff git adds to -next from the patch
in -fixes.

Note that this doesn't show up in git's merge diff (and hence is also
not handled by git rerere), which adds to the reasons why I'd like to
fix this with a verbose backmerge. The git merge diff only shows a
bunch of trivial conflicts of the "code changed in lines next to each
another" kind.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-24 18:17:12 +02:00
Paulo Zanoni
57df2ae9df drm/i915: BUG() on unexpected HDMI register
This should never happen, but the silent "return" makes me wonder
every time I try to debug InfoFrame bugs, so promote this to BUG() to
make sure people will complain if we ever break this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-24 16:24:20 +02:00
Dave Airlie
017a27e7f5 Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Daniel writes:
Essentially just flush my -fixes queue before I head off to xdc.
- gen2 regression fixer, we've enabled the lvds stuff too late. Not
  causing any known issues, but this restores the sequence before a
  refactor that landed in 3.5, and lvds is a fickle beast. And seriously,
  who runs gen2 still ...
- downgrade a BUG to a WARN - we haven't root-caused/fixed the underlying
  issue yet, but this should help bug reporters quite a bit.
- properly disable hdmi audio - we've lost track of this, which resulted
  in the alsa driver again losing track of the unplug event.

* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: HDMI - Clear Audio Enable bit for Hot Plug
  drm/i915: Reduce a pin-leak BUG into a WARN
  drm/i915: enable lvds pin pairs before dpll on gen2
2012-09-21 20:46:01 +10:00
Dave Airlie
6c06d608ec drm/nouveau: add dmi quirk for gpio reset
This fixes the gpio reset problem so the Retina MBP works, but avoids
breaking the Dell systems. Ben will work on a better solution for 3.7.

Tested by me on retina MBP.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-09-21 10:17:15 -04:00
Dave Airlie
8e910d08a2 Merge branch 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
fixes a resume regression on pre-r6xx asics.

* 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: Prevent leak of scratch register on resume from suspend
2012-09-21 06:50:40 +10:00
Alex Deucher
9642ac0e64 drm/radeon: make non-DP PPLL sharing more robust
Compare the adjusted clock as well as the crtc mode
clock.  This handles cases where the driver adjusts
the clock for specific special cases.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 13:10:44 -04:00
Alex Deucher
5df3196bac drm/radeon: store the encoder in the radeon_crtc
This saves lots of lookups later.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 13:10:44 -04:00
Alex Deucher
19eca43e5a drm/radeon: rework crtc pll setup to better support PPLL sharing
We need the calculate the pixel clock before allocating a PPLL
in order to insure the clocks really match.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 13:10:44 -04:00
Alex Deucher
2f454cf126 drm/radeon: allow PPLL sharing on non-DP displays
If several non-DP displays use the same pixel clock
we can use the same PPLL for all of them.  If all
relevant displays have the same pixel clock, this
allows the driver to:
- use fewer PPLLs which saves power
- support more than two non-DP displays on DCE4+

The current drm modesetting infrastructure doesn't
really provide a good framework for validating combinations
that work or won't work, so it's possible you could go from
a working configuration to a non-working one by changing the
mode a one of the displays.  However, there this is better
than what was there before.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 13:10:44 -04:00