John Crispin
2636562594
MIPS: lantiq: rework external irq code
...
This code makes the irqs used by the EIU loadable from the DT. Additionally we
add a helper that allows the pinctrl layer to map external irqs to real irq
numbers.
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4818/
2013-02-17 00:15:18 +01:00
John Crispin
79d61a046b
MIPS: Lantiq: Fix cp0_perfcount_irq mapping
...
The introduction of the OF support broke the cp0_perfcount_irq mapping. This
resulted in oprofile not working anymore.
Offending commit is :
commit 3645da0276blogic@openwrt.org >
Date: Tue Apr 17 10:18:32 2012 +0200
OF: MIPS: lantiq: implement irq_domain support
Signed-off-by: Conor O'Gorman <i@conorogorman.net >
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4875/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2013-01-30 21:28:28 +01:00
John Crispin
70ec9054e7
MIPS: lantiq: external irq sources are not loaded properly
...
Support for the external interrupt unit was broken when the code was converted
to devicetree support.
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4231/
2012-08-23 00:08:17 +02:00
John Crispin
9c1628b603
MIPS: lantiq: dont register irq_chip for the irq cascade
...
We dont want to register the irq_chip for the MIPS IRQ cascade.
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4230/
2012-08-23 00:08:17 +02:00
John Crispin
c2c9c788b9
MIPS: lantiq: timer irq can be different to 7
...
The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq
code to be able to handle this.
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4229/
2012-08-23 00:08:17 +02:00
John Crispin
61fa969f27
MIPS: lantiq: split up IRQ IM ranges
...
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4237/
2012-08-23 00:08:17 +02:00
John Crispin
3645da0276
OF: MIPS: lantiq: implement irq_domain support
...
Add support for irq_domain on lantiq socs. The conversion is straight forward
as the ICU found inside the socs allows the usage of irq_domain_add_linear.
Harware IRQ 0->7 are the generic MIPS IRQs. 8->199 are the Lantiq IRQ Modules.
Our irq_chip callbacks need to substract 8 (MIPS_CPU_IRQ_CASCADE) from d->hwirq
to find out the correct offset into the Interrupt Modules register range.
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Grant Likely <grant.likely@secretlab.ca >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3802/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2012-05-21 14:31:50 +01:00
John Crispin
a8d096ef78
MIPS: lantiq: add ipi handlers to make vsmp work
...
Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work
on lantiq socs. The code is based on the malta implementation.
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3704/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2012-05-15 17:49:21 +02:00
John Crispin
59c1157984
MIPS: lantiq: enable oprofile support on lantiq targets
...
This patch sets the performance counters irq on Lantiq SoCs.
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3720/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2012-05-15 17:49:21 +02:00
John Crispin
16f70b561d
MIPS: lantiq: clear all irqs properly on boot
...
Due to missing brackets, the irq modules were not properly reset on boot.
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3719/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2012-05-15 17:49:21 +02:00
Ralf Baechle
39b741431a
Merge branch 'next/generic' into mips-for-linux-next
2012-01-11 15:41:47 +01:00
Yong Zhang
8b5690f884
MIPS: irq: Remove IRQF_DISABLED
...
Since commit [e58aa3d2b738a50ahttps://patchwork.linux-mips.org/patch/2835/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2011-12-07 22:03:45 +00:00
Ralf Baechle
ab75dc02c1
MIPS: Fix up inconsistency in panic() string argument.
...
Panic() invokes printk() to add a \n internally, so panic arguments should
not themselves end in \n. Panic invocations in arch/mips and elsewhere
are inconsistently sometimes terminating in \n, sometimes not.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2011-12-07 22:01:45 +00:00
John Crispin
77fbdb30f0
MIPS: Lantiq: Fix external interrupt sources
...
The irq base offset needs to be ignored when matching irqs to external
interrupt pins. Taking the offset into account resulted in the EIU not
being brought up properly.
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2616/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2011-09-21 17:53:12 +02:00
John Crispin
171bb2f19e
MIPS: Lantiq: Add initial support for Lantiq SoCs
...
Add initial support for Mips based SoCs made by Lantiq. This series will add
support for the XWAY family.
The series allows booting a minimal system using a initramfs or NOR. Missing
drivers and support for Amazon and GPON family will be provided in a later
series.
[Ralf: Remove some cargo cult programming and fixed formatting.]
Signed-off-by: John Crispin <blogic@openwrt.org >
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com >
Signed-off-by: David Daney <ddaney@caviumnetworks.com >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2252/
Patchwork: https://patchwork.linux-mips.org/patch/2371/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2011-05-19 09:55:41 +01:00
