Yintian Tao
11a88c2e92
drm/powerplay: enable dpm under pass-through
...
Repeat enable dpm under pass-through because there is no actually
hardware-fini and real power-off when guest vm shutdown or reboot.
Otherwise, under pass-through it will be failed to populate populate
and upload SCLK MCLK DPM levels due to zero of pcie_speed_table.count.
Signed-off-by: Yintian Tao <yttao@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-08-21 14:18:21 -05:00
Dave Airlie
940fbcb73f
Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-next
...
Fixes for 4.19:
- Fix UVD 7.2 instance handling
- Fix UVD 7.2 harvesting
- GPU scheduler fix for when a process is killed
- TTM cleanups
- amdgpu CS bo_list fixes
- Powerplay fixes for polaris12 and CZ/ST
- DC fixes for link training certain HMDs
- DC fix for vega10 blank screen in certain cases
From: Alex Deucher <alexdeucher@gmail.com >
Signed-off-by: Dave Airlie <airlied@redhat.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180801222906.1016-1-alexander.deucher@amd.com
2018-08-08 06:22:23 +10:00
Rex Zhu
8a50bb47a8
drm/amd/pp: Convert voltage unit in mV*4 to mV on CZ/ST
...
the voltage showed in debugfs and hwmon should be in mV
Reviewed-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
Cc: stable@vger.kernel.org
2018-07-31 16:58:06 -05:00
Rex Zhu
90983631a6
drm/amd/pp: Delete unused temp variables
...
Only delete the dead temp variables in Polaris.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-31 16:58:06 -05:00
Rex Zhu
2d227ec2c1
drm/amd/pp/Polaris12: Fix a chunk of registers missed to program
...
DIDTConfig_Polaris12[] table missed a big chunk of data.
Pointed by aidan.fabius <aidan.fabius@coreavi.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
Cc: stable@vger.kernel.org
2018-07-31 16:58:02 -05:00
Dave Airlie
3fce461827
BackMerge v4.18-rc7 into drm-next
...
rmk requested this for armada and I think we've had a few
conflicts build up.
Signed-off-by: Dave Airlie <airlied@redhat.com >
2018-07-30 10:39:22 +10:00
Evan Quan
92859e0d5c
drm/amd/powerplay: allow slow switch only if NBPState enabled v2
...
Otherwise there may be potential SMU performance issues.
v2: fix commit description and coding style
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Rex Zhu <rex.zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-24 15:14:35 -05:00
Evan Quan
f132d56162
drm/amd/powerplay: correct the argument for PPSMC_MSG_SetUclkFastSwitch
...
The argument was set wrongly. Fast/slow switch was asked when there is
actually a slow/fast switch needed.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Rex Zhu <rex.zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-24 15:14:25 -05:00
Evan Quan
59a8348fc5
drm/amd/powerplay: slow UCLK switch when multiple displays not in sync
...
Slow switch for UCLK when there is multiple displays and they are
not in sync.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Rex Zhu <rex.zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-24 15:14:14 -05:00
Rex Zhu
97e8f102f5
drm/amd/pp: Set Max clock level to display by default
...
avoid the error in dmesg:
[drm:dm_pp_get_static_clocks]
*ERROR* DM_PPLIB: invalid powerlevel state: 0!
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Reviewed-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-20 14:24:00 -05:00
Rex Zhu
a0c3bf0ff4
drm/amd/pp: Update clk with od setting when set power state
...
This can fix the issue resume from S3, the user's OD setting
were reverted to default.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-20 14:23:53 -05:00
Rex Zhu
88de542e42
drm/amd/pp: Read vbios vddc limit before use them
...
Use the vddc limit before read them from vbios
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-20 14:23:45 -05:00
Evan Quan
1ce0688f3f
drm/amd/powerplay: fixed uninitialized value
...
The 'result' is not initialized correctly. It causes the API
return an error code even on success.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Huang Rui <ray.huang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
Cc: stable@vger.kernel.org
2018-07-19 13:56:43 -05:00
Alex Deucher
c64fb6dade
drm/amdgpu/powerplay: use irq source defines for smu7 sources
...
Use the newly added irq source defines rather than magic numbers
for smu7 thermal interrupts.
Rewiewed-by: Chunming Zhou <david1.zhou@amd.com >
Reviewed-by: Rex Zhu <rezhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-19 13:53:55 -05:00
Eric Huang
8415afbd86
Revert "drm/amd/powerplay: fix performance drop on Vega10"
...
This reverts commit b87079ec7b
.
SMU FW team ask to remove this version specific code.
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-16 15:29:29 -05:00
Alex Deucher
59f20f5a0c
drm/amdgpu/pp: switch smu callback type for get_argument()
...
return a uint32_t rather than an int to properly reflect
what the function does.
Reviewed-by: Rex Zhu <rezhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-16 11:39:28 -05:00
Alex Deucher
ce7577a219
drm/amdgpu/pp: split out common smumgr smu9 code
...
Split out the shared smumgr code for vega10 and 12
so we don't have duplicate code for both.
Reviewed-by: Rex Zhu <rezhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-16 11:39:22 -05:00
Alex Deucher
26094c0293
drm/amdgpu/pp: remove dead vega12 code
...
Commented out.
Reviewed-by: Rex Zhu <rezhu@amd.com >
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-16 11:39:16 -05:00
Alex Deucher
d92867122c
drm/amdgpu/pp/smu7: cache smu firmware toc
...
Rather than calculating it everytime we rebuild the toc
buffer, calculate it once initially and then just copy
the cached results to the vram buffer.
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:52:58 -05:00
Alex Deucher
82088d5d7d
drm/amdgpu/pp/smu7: remove local mc_addr variable
...
use the structure member directly.
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:52:58 -05:00
Alex Deucher
2bce4be037
drm/amdgpu/pp/smu7: drop unused values in smu data structure
...
use kaddr directly rather than secondary variable.
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:52:57 -05:00
Alex Deucher
3d75a8b689
drm/amdgpu/pp/smu7: use a local variable for toc indexing
...
Rather than using the index variable stored in vram. If
the device fails to come back online after a resume cycle,
reads from vram will return all 1s which will cause a
segfault. Based on a patch from Thomas Martitz <kugel@rockbox.org >.
This avoids the segfault, but we still need to sort out
why the GPU does not come back online after a resume.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105760
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:52:50 -05:00
Andrey Grodzovsky
44a99b65fc
drm/amd: Use newly added interrupt source defs for SOC15.
...
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com >
Reviewed-by: Christian König <christian.koenig@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:45:43 -05:00
Andrey Grodzovsky
091aec0b4e
drm/amd: Use newly added interrupt source defs for VI v3.
...
v2: Rebase
v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com >
Reviewed-by: Christian König <christian.koenig@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:45:30 -05:00
Evan Quan
ed515ce274
drm/amd/powerplay: convert the sclk/mclk into Mhz for comparation
...
Convert the clocks into right Mhz unit. Otherwise, it will miss
the equal situation.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Huang Rui <ray.huang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:45:16 -05:00
Evan Quan
3f2e6bf89c
drm/amd/powerplay: no need to mask workable gfxoff feature for vega12
...
Gfxoff feature for vega12 is workable. So, there is no need to
mask it any more.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:45:08 -05:00
Evan Quan
991a6b32ce
drm/amd/powerplay: add vega12 SMU gfxoff support v3
...
Export apis for enabling/disabling SMU gfxoff support.
v2: fit the latest gfxoff support framework
v3: add feature_mask control
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Huang Rui <ray.huang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-13 14:45:01 -05:00
Alex Deucher
02ce6ce2e1
drm/amdgpu/pp/smu7: use a local variable for toc indexing
...
Rather than using the index variable stored in vram. If
the device fails to come back online after a resume cycle,
reads from vram will return all 1s which will cause a
segfault. Based on a patch from Thomas Martitz <kugel@rockbox.org >.
This avoids the segfault, but we still need to sort out
why the GPU does not come back online after a resume.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105760
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
Cc: stable@vger.kernel.org
2018-07-13 11:42:45 -05:00
kbuild test robot
0d7f824b33
drm/amd/pp: fix semicolon.cocci warnings
...
drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:1209:17-18: Unneeded semicolon
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
Fixes: ea870e4441
("drm/amd/pp: Export notify_smu_enable_pwe to display")
CC: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: kbuild test robot <fengguang.wu@intel.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-10 14:19:02 -05:00
Harry Wentland
c3cb424a08
drm/amd/pp: Send khz clock values to DC for smu7/8
...
The previous change wasn't covering smu 7 and 8 and therefore DC was
seeing wrong clock values.
This fixes an issue where the pipes seem to hang with a 4k DP and 1080p
HDMI display.
Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined")
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Cc:rex.zhu@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-10 14:17:59 -05:00
Rex Zhu
ed0926647d
drm/amd/pp: Convert 10KHz to KHz as variable name
...
The default clock unit in powerplay is 10KHz.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-10 14:16:53 -05:00
Rex Zhu
20582319bc
drm/amd/pp: Remove the same struct define in powerplay
...
delete the same struct define in powerplay, share the struct
with display.
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:40:02 -05:00
Rex Zhu
ea870e4441
drm/amd/pp: Export notify_smu_enable_pwe to display
...
Display can notify smu to enable pwe after gpu suspend.
It is used in case when display resumes from S3 and wants to start
audio driver by enabling pwe
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:40:00 -05:00
Rex Zhu
860c15e903
drm/amd/pp: Remove duplicate code in vega12_hwmgr.c
...
use smu_helper function smu_set_watermarks_for_clocks_ranges
in vega12_set_watermarks_for_clocks_ranges.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:57 -05:00
Rex Zhu
99c5e27d33
drm/amd/pp: Refine the interface exported to display
...
use void * as function parameter type in order for extension.
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:57 -05:00
rex zhu
7d8d968dac
drm/amd/pp: Switch the tolerable latency for display
...
Select the lowest MCLK frequency that is within
the tolerable latency defined in DISPALY
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Acked-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:56 -05:00
Rex Zhu
6eb9d60304
drm/amd/pp: Memory Latency is always 25us on Vega10
...
For HBM, 25us latency is enough for memory clock switch.
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Acked-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:55 -05:00
Rex Zhu
23ec3d1479
drm/amd/pp: Convert clock unit to KHz as defined
...
Convert clock unit 10KHz to KHz as the data sturct defined.
e.g.
struct pp_clock_with_latency {
uint32_t clocks_in_khz;
uint32_t latency_in_us;
};
Meanwhile revert the same conversion in display side.
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Acked-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:55 -05:00
Alex Deucher
ed54d954e5
drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1
...
Should be using PCIELaneLow for the low clock level.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:52 -05:00
Alex Deucher
9861023c29
drm/amdgpu/pp: fix copy paste typo in smu7_init_dpm_defaults
...
Should be mclk rather than sclk.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:52 -05:00
Alex Deucher
594c34cc6f
drm/amdgpu/pp: fix endian swapping in atomctrl_get_voltage_range
...
Need to swap before doing arthimetic on the values.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:51 -05:00
Alex Deucher
c9037d4439
drm/amdgpu/pp: add missing byte swapping in process_pptables_v1_0.c
...
Values need to be swapped on big endian.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:39:51 -05:00
Evan Quan
0c3d017445
drm/amd/powerplay: cosmetic fix
...
Fix coding style and drop unused variable.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:38:56 -05:00
Evan Quan
6ad87101f3
drm/amd/powerplay: correct vega12 thermal support as true
...
Thermal support is enabled on vega12.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:38:56 -05:00
Evan Quan
28a7b4f449
drm/amd/powerplay: set vega12 pre display configurations
...
Set num_displays to 0 and force uclk high as part of the mode
set sequence.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:38:56 -05:00
Evan Quan
e17c7f92b2
drm/amd/powerplay: apply clocks adjust rules on power state change
...
This add the apply_clocks_adjust_rules callback which is used
to validate the clock settings on a power state change.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:38:55 -05:00
Evan Quan
a0a59c8fc7
drm/amd/powerplay: correct vega12 max num of dpm level
...
Use MAX_NUM_CLOCKS instead of VG12_PSUEDO* macros for
the max number of dpm levels.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:38:55 -05:00
Evan Quan
3022256180
drm/amd/powerplay: drop unnecessary uclk hard min setting
...
We don't need to set uclk hard min here because this will
be set with other clocks on power state change.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:38:55 -05:00
Evan Quan
ac32b06ace
drm/amd/powerplay: correct smc display config for multi monitor
...
Need to take into account multi-head with synced displays.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:38:54 -05:00
Evan Quan
f74aa69d0a
drm/amd/powerplay: initialize uvd/vce powergate status v4
...
On UVD/VCE dpm enabled/disabled, the powergate status will be
set as false/true. So that we will not try to ungate/gate them(
enable/disable their dpm) again.
v2: added check for uvd/vce powergate status before gating
v3: fix typo in description
v4: warning fix (Alex)
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-05 16:38:54 -05:00