Some operations must ensure that the guest is not running with stale
data, but if the guest is halted, then the update can wait until another
event happens. kvm_make_all_requests() currently doesn't wake up, so we
can mark all requests used with it.
First 8 bits were arbitrarily reserved for request numbers.
Most uses of requests have the request type as a constant, so a compiler
will optimize the '&'.
An alternative would be to have an inline function that would return
whether the request needs a wake-up or not, but I like this one better
even though it might produce worse assembly.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The arm64 module PLT code allocates all PLT entries in a single core
section, since the overhead of having a separate init PLT section is
not justified by the small number of PLT entries usually required for
init code.
However, the core and init module regions are allocated independently,
and there is a corner case where the core region may be allocated from
the VMALLOC region if the dedicated module region is exhausted, but the
init region, being much smaller, can still be allocated from the module
region. This leads to relocation failures if the distance between those
regions exceeds 128 MB. (In fact, this corner case is highly unlikely to
occur on arm64, but the issue has been observed on ARM, whose module
region is much smaller).
So split the core and init PLT regions, and name the latter ".init.plt"
so it gets allocated along with (and sufficiently close to) the .init
sections that it serves. Also, given that init PLT entries may need to
be emitted for branches that target the core module, modify the logic
that disregards defined symbols to only disregard symbols that are
defined in the same section as the relocated branch instruction.
Since there may now be two PLT entries associated with each entry in
the symbol table, we can no longer hijack the symbol::st_size fields
to record the addresses of PLT entries as we emit them for zero-addend
relocations. So instead, perform an explicit comparison to check for
duplicate entries.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Commit f1b36dcb5c ("arm64: pmuv3: handle !PMUv3 when probing") is
a little too restrictive, and prevents the use of of backwards
compatible PMUv3 extenstions, which have a PMUver value other than 1.
For instance, ARMv8.1 PMU extensions (as implemented by ThunderX2) are
reported with PMUver value 4.
Per the usual ID register principles, at least 0x1-0x7 imply a
PMUv3-compatible PMU. It's not currently clear whether 0x8-0xe imply the
same.
For the time being, treat the value as signed, and with 0x1-0x7 treated
as meaning PMUv3 is implemented. This may be relaxed by future patches.
Reported-by: Jayachandran C <jnair@caviumnetworks.com>
Tested-by: Jayachandran C <jnair@caviumnetworks.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and
Posting") defines rules for PCI configuration space transactions ordering
and posting, that state that configuration writes are non-posted
transactions.
This rule is reinforced by the ARM v8 architecture reference manual (issue
A.k, Early Write Acknowledgment) that explicitly recommends that No Early
Write Acknowledgment attribute should be used to map PCI configuration
(write) transactions.
Current ioremap interface on ARM64 implements mapping functions where the
Early Write Acknowledgment hint is enabled, so they cannot be used to map
PCI configuration space in a PCI specs compliant way.
Implement an ARM64 specific pci_remap_cfgspace() interface that allows to
map PCI config region with nGnRnE attributes, providing a remap function
that complies with PCI specifications and the ARMv8 architecture reference
manual recommendations.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[k.kozlowski: Split patch per ARM and ARM64]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
We now trap accesses to CNTVCT_EL0 when the counter is broken
enough to require the kernel to mediate the access. But it
turns out that some existing userspace (such as OpenMPI) do
probe for the counter frequency, leading to an UNDEF exception
as CNTVCT_EL0 and CNTFRQ_EL0 share the same control bit.
The fix is to handle the exception the same way we do for CNTVCT_EL0.
Fixes: a86bd139f2 ("arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled")
Reported-by: Hanjun Guo <guohanjun@huawei.com>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[k.kozlowski: Split patch per ARM and ARM64]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch adds the panel device tree node for s6e3hf2 display
controller to TM2e dts.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
A function in kernel/bpf/syscall.c which got a bug fix in 'net'
was moved to kernel/bpf/verifier.c in 'net-next'.
Signed-off-by: David S. Miller <davem@davemloft.net>
With arch_setup_dma_ops now being called late during device's probe after
the device's iommu is probed, the notifier trick required to handle the
early setup of dma_ops before the iommu group gets created is not
required. So removing the notifier's here.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
[rm: clean up even more]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Starting to leave behind the legacy of the pci_mmap_page_range() interface
which takes "user-visible" BAR addresses. This takes just the resource and
offset.
For now, both APIs coexist and depending on the platform, one is
implemented as a wrapper around the other.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
mvebu defconfig64 for 4.12 (part 2)
Select two new drivers for ARM64 mvebu SoCs:
- Xenon SDHCI controller on Armada 37xx and Armada 7K/8K
- Safexcel crypto engine on Armada 7K/8K
* tag 'mvebu-defconfig64-4.12-2' of git://git.infradead.org/linux-mvebu:
arm64: defconfig: enable the Safexcel crypto engine as a module
arm64: configs: enable SDHCI driver for Xenon
Signed-off-by: Olof Johansson <olof@lixom.net>
Samsung ARM64 update for v4.12:
1. Exynos power management drivers support now ARMv8 SoC - Exynos5433 - so
select them in ARCH_EXYNOS.
2. Enable few Exynos drivers for supported ARMv8 SoCs.
* tag 'samsung-soc64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: defconfig: Enable video, DRM and LPASS drivers for Exynos5433 and Exynos7
arm64: exynos: Enable Exynos PMU and PM domains drivers
Signed-off-by: Olof Johansson <olof@lixom.net>
mvebu dt64 for 4.12 (part 2)
- crypto engine description for the Armada 7k/8k SoCs and the boards
using it
- SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards
using it
* tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu:
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
Signed-off-by: Olof Johansson <olof@lixom.net>
ARM64: DT: Hisilicon SoC DT updates for 4.12
- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins
* tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
arm64: dts: hi6220: Reset the mmc hosts
Signed-off-by: Olof Johansson <olof@lixom.net>
ZTE arm64 device tree updates for 4.12:
- Add mmc devices for ZX296718 SoC and enable those available on
zx296718-evb board.
- Add VOU controller device, output devices HDMI and TVENC, and enable
display support for zx296718-evb board.
- Remove pll_vga clock from ZX296718 device tree, as it's not a fixed
rate clock.
* tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: zte: add tvenc device for zx296718
arm64: dts: zte: add vou and hdmi devices for zx296718
arm64: dts: zte: add mmc devices for zx296718
arm64: dts: zte: remove zx296718 pll_vga clock
Signed-off-by: Olof Johansson <olof@lixom.net>
Freescale arm64 device tree updates for 4.12:
- Add support of LS2088A SoC, which is a derivative of existing
LS2080A SoC, and the major difference is on ARM cores.
- Add support of LS1088A SoC which includes eight Cortex-A53 cores
with 32 KB L1 D-cache and I-cache respectively.
- Add crypto and thermal device support for LS1012A platform.
- Add ECC register region for SATA device on LS1012A, LS1043A and
LS1046A platforms.
* tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards
dt-bindings: clockgen: Add compatible string for LS1088A
arm64: dts: Add support for FSL's LS1088A SoC
arm64: dts: ls1012a: add crypto node
arm64: dts: ls1012a: add thermal monitor node
arm64: dts: updated sata node on ls1012a platform
arm64: dts: added ecc register address to sata node on ls1046a
arm64: dts: added ecc register address to sata node on ls1043a
arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC
arm64: dts: freescale: ls2080a: Split devicetree for code resuability
dt-bindings: Add compatible for LS2088A QDS and RDB board
Signed-off-by: Olof Johansson <olof@lixom.net>
Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the
default memory definition on the px5 eval board. While the bootloader
should already override it with the actual amount, it's better to not
carry around wrong values.
* tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: rockchip: add RK3328 eavluation board devicetree
dt-bindings: document rockchip rk3328-evb board
arm64: dts: rockchip: add core dtsi file for RK3328 SoCs
dt-bindings: add binding for rk3328-grf
Signed-off-by: Olof Johansson <olof@lixom.net>
Samsung DeviceTree ARM64 update for v4.12:
1. Add IR, touchscreen and panel to TM2/TM2E boards.
2. Add proper clock frequency properties to DSI nodes.
* tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add the burst and esc clock frequency properties to DSI node
arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 board
arm64: dts: exynos: Add stmfts touchscreen node for TM2 and TM2E
arm64: dts: exynos: Enable ir-spi in the TM2 and TM2E boards
Signed-off-by: Olof Johansson <olof@lixom.net>
Second Round of Renesas ARM64 Based SoC DT Updates for v4.12
Corrections:
* r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC
Cleanup:
* Drop _clk suffix from X12 clock node name for r8a7795 SoC
Enhancements:
* Add reset control properties for r8a779[56]
* tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name
arm64: dts: r8a7796: Add reset control properties
arm64: dts: r8a7795: Add reset control properties
arm64: dts: r8a7795: Correct SATA device size to 2MiB
Signed-off-by: Olof Johansson <olof@lixom.net>
arm64: tegra: Device tree changes for v4.12-rc1
This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
SDHCI and GPIO. It also enables various features on the P2771 devkit.
A small fix is made to the compatible string list for the flow
controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.
* tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Update the Tegra132 flowctrl compatible string
arm64: tegra: Add GPU node for Tegra186
arm64: tegra: Enable IOMMU for host1x on Tegra210
arm64: tegra: Enable VIC on Tegra210
arm64: tegra: Add GPIO expanders on P2771
arm64: tegra: Add power monitors on P2771
arm64: tegra: Add GPIO keys on P2771
arm64: tegra: Enable current monitors on P3310
arm64: tegra: Enable SD/MMC slot on P2771
arm64: tegra: Enable SDHCI controllers on P3110
arm64: tegra: Add initial power tree for P3310
arm64: tegra: Enable ethernet on P3310
arm64: tegra: Enable I2C controllers on P3310
arm64: tegra: Invert the PMC interrupt on P3310
arm64: tegra: Add ethernet support for Tegra186
arm64: tegra: Add PMC controller on Tegra186
Signed-off-by: Olof Johansson <olof@lixom.net>
Allwinner H5 DT changes for 4.12
H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.
We then have patches to support the H5 boards on top.
* tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu
arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
arm64: allwinner: h5: add support for the Orange Pi PC 2 board
arm64: allwinner: h5: add Allwinner H5 .dtsi
ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
arm: sun8i: h3: split Allwinner H3 .dtsi
arm: sun8i: h3: correct the GIC compatible in H3 to gic-400
arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>
Allwinner arm64 DT changes for 4.12
Some patches to enable the PRCM block in the A64
* tag 'sunxi-dt64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: a64: add R_PIO pinctrl node
arm64: allwinner: a64: add r_ccu node
Signed-off-by: Olof Johansson <olof@lixom.net>
Allwinner arm64 config changes for 4.12
Two patches to change our Kconfig option and add new options in the
defconfig.
* tag 'sunxi-config64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: defconfig: add Allwinner USB PHY
arm64: only select PINCTRL for Allwinner platforms
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit a8d4636f96 ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.
Commit 9a802431c5 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.
This patch adds the information about L1 and L2 caches on all variants
of Juno platform.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This patch fixes the following set of warnings on juno.
smb@08000000 unit name should not have leading 0s
sysctl@020000 simple-bus unit address format error, expected "20000"
apbregs@010000 simple-bus unit address format error, expected "10000"
mmci@050000 simple-bus unit address format error, expected "50000"
kmi@060000 simple-bus unit address format error, expected "60000"
kmi@070000 simple-bus unit address format error, expected "70000"
wdt@0f0000 simple-bus unit address format error, expected "f0000"
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Johan Hedberg says:
====================
pull request: bluetooth-next 2017-04-14
Here's the main batch of Bluetooth & 802.15.4 patches for the 4.12
kernel.
- Many fixes to 6LoWPAN, in particular for BLE
- New CA8210 IEEE 802.15.4 device driver (accounting for most of the
lines of code added in this pull request)
- Added Nokia Bluetooth (UART) HCI driver
- Some serdev & TTY changes that are dependencies for the Nokia
driver (with acks from relevant maintainers and an agreement that
these come through the bluetooth tree)
- Support for new Intel Bluetooth device
- Various other minor cleanups/fixes here and there
Please let me know if there are any issues pulling. Thanks.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Unlike normal compat syscall variants, it is needed only for
biarch architectures that have different alignement requirements for
u64 in 32bit and 64bit ABI *and* have __put_user() that won't handle
a store of 64bit value at 32bit-aligned address. We used to have one
such (ia64), but its biarch support has been gone since 2010 (after
being broken in 2008, which went unnoticed since nobody had been using
it).
It had escaped removal at the same time only because back in 2004
a patch that switched several syscalls on amd64 from private wrappers to
generic compat ones had switched to use of compat_sys_getdents64(), which
hadn't needed (or used) a compat wrapper on amd64.
Let's bury it - it's at least 7 years overdue.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Pull ARM SoC fixes from Olof Johansson:
"Again, a batch that's been sitting a couple of weeks, mostly because
I anticipated a bit more material but it didn't show up -- which is
good.
These are all your garden variety fixes for ARM platforms.
The most visible issue fixed here is probably the SMP reset issue on
OMAP, the rest are minor stuff"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
arm64: allwinner: a64: add pmu0 regs for USB PHY
ARM: OMAP2+: omap_device: Sync omap_device and pm_runtime after probe defer
reset: add exported __reset_control_get, return NULL if optional
ARM: orion5x: only call into phylib when available
ARM: omap2+: Revert omap-smp.c changes resetting CPU1 during boot
ARM: dts: am335x-evmsk: adjust mmc2 param to allow suspend
ARM: dts: ti: fix PCI bus dtc warnings
ARM: dts: am335x-baltos: disable EEE for Atheros 8035 PHY
ARM: dts: OMAP3: Fix MFG ID EEPROM
ARM: sun8i: a33: add operating-points-v2 property to all nodes
ARM: sun8i: a33: remove highest OPP to fix CPU crashes
The Safexcel EIP197 cryptographic engine is used on some Marvell SoCs,
such as Armada 7040 and Armada 8040. Enable this driver as a module in
the ARM64 defconfig.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Since bbb56c2722 ("arm64: Add detection code for broken .inst support
in binutils"), running any make target that doesn't involve the cross
compiler results in a spurious warning:
$ make ARCH=arm64 menuconfig
arch/arm64/Makefile:43: Detected assembler with broken .inst; disassembly will be unreliable
while
$ make ARCH=arm64 CROSS_COMPILE=aarch64-arm-linux- menuconfig
is silent (assuming your compiler is not affected). That's because
the code that tests for the workaround is always run, irrespective
of the current configuration being available or not.
An easy fix is to make the detection conditional on CONFIG_ARM64
being defined, which is only the case when actually building
something.
Fixes: bbb56c2722 ("arm64: Add detection code for broken .inst support in binutils")
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Enable the cryptographic engine available in the CP110 master on the
Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we
do not support multiple cryptographic engines yet.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add the description of the crypto engine hardware block for the Marvell
Armada 7k and Armada 8k processors; for both the CP110 slave and master.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Now that we have a framework to handle the ACPI bits, make the PMUv3
code use this. The framework is a little different to what was
originally envisaged, and we can drop some unused support code in the
process of moving over to it.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
[will: make armv8_pmu_driver_init static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
When probing via ACPI, we won't know up-front whether a CPU has a PMUv3
compatible PMU. Thus we need to consult ID registers during probe time.
This patch updates our PMUv3 probing code to test for the presence of
PMUv3 functionality before touching an PMUv3-specific registers, and
before updating the struct arm_pmu with PMUv3 data.
When a PMUv3-compatible PMU is not present, probing will return -ENODEV.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Currently the ACPI parking protocol code needs to parse each CPU's MADT
GICC table to extract the mailbox address and so on. Each time we parse
a GICC table, we call back to the parking protocol code to parse it.
This has been fine so far, but we're about to have more code that needs
to extract data from the GICC tables, and adding a callback for each
user is going to get unwieldy.
Instead, this patch ensures that we stash a copy of each CPU's GICC
table at boot time, such that anything needing to parse it can later
request it. This will allow for other parsers of GICC, and for
simplification to the ACPI parking protocol code. Note that we must
store a copy, rather than a pointer, since the core ACPI code
temporarily maps/unmaps tables while iterating over them.
Since we parse the MADT before we know how many CPUs we have (and hence
before we setup the percpu areas), we must use an NR_CPUS sized array.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
