This binding is for FMan MDIO, it covers FMan v2 & FMan v3.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[scottwood@freescale.com: mark interrupts required only for external]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Merge "Samsung 2nd DT updates for v3.20" from Kukjin Kim:
- for all of Samsung SoCs
: use generic power domain bindings
: add 'dr_mode' property for hsotg/dwc2 devices
- exynos3250-rinato and exynos3250-monk
: add regulator-haptic
- exynos5422-odroidxu3
: reduce total RAM by 22 MiB because last 22 MiB
for secure monitor cannot be accessed by kernel
: add on-board INA231 sensors and LDO26 of PMIC
for the sensors
* tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: reduce total RAM by 22 MiB for exynos5422-odroidxu3
ARM: dts: add on-board INA231 sensors for exynos5422-odroidxu3
ARM: dts: Add regulator-haptic node for exynos3250-monk
ARM: dts: Add regulator-haptic node for exynos3250-rinato
ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
ARM: dts: convert to generic power domain bindings for exynos DT
Signed-off-by: Olof Johansson <olof@lixom.net>
Add support for the larger fifo found on sun5i and sun6i, having a separate
compatible for the ir found on sun5i & sun6i also is useful if we ever want
to add ir transmit support, because the sun5i & sun6i version do not have
transmit support.
Note this commits also adds checking for the end-of-packet interrupt flag
(which was already enabled), as the fifo-data-available interrupt flag only
gets set when the trigger-level is exceeded. So far we've been getting away
with not doing this because of the low trigger-level, but this is something
which we should have done since day one.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
The Conexant CX92755 SoC provides 8 32-bit timers as part of its so called
"Agent Communication" block. Timers can be configures either as free running or
one shot. Each timer has a dedicated interrupt source in the CX92755 interrupts
controller. The first timer (Timer A) can also be configured as watchdog.
This commit adds devicetree binding definition of this hardware module. The
binding defined here should be reusable for other SoCs in the Digicolor series.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.
This driver provides the basic timer functionnality as a backup for the local
timers at sleep time.
The timer belongs to the alive subsystem. It includes two programmables 64 bits
timer channels but the driver only uses 32bits. It works with two operations
mode: free running and user defined count.
Programing sequence:
1. Timer initialization:
* Disable the timer by writing '0' to the CONTROLREG register
* Program the timer mode by writing the mode to the CONTROLREG register
* Set the interrupt mask
2. Setting the count value:
* Load the count value to the registers COUNT0 and COUNT1 (not used).
3. Enable the timer
* Write '1' to the CONTROLREG register with the mode (free running or user)
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
The SDHCI unit used on the Armada 38x needs using an extra register to
do specific clock adjustments in order to support the SDR50 and DDR50
modes. This patch extends the binding to allow using this register.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
NFC: 3.20 first pull request
This is the first NFC pull request for 3.20.
With this one we have:
- Secure element support for the ST Micro st21nfca driver. This depends
on a few HCI internal changes in order for example to support more
than one secure element per controller.
- ACPI support for NXP's pn544 HCI driver. This controller is found on
many x86 SoCs and is typically enumerated on the ACPI bus there.
- A few st21nfca and st21nfcb fixes.
Signed-off-by: David S. Miller <davem@davemloft.net>
This backmerges drm-fixes into drm-next mainly for the amdkfd
stuff, I'm not 100% confident, but it builds and the amdkfd
folks can fix anything up.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Conflicts:
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
This patch fix multiple words such as "the the" and "which which"
in Documentation/devicetree.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
The "wlf,wm8912" compatible string is used for wm8912, which
share driver with wm8904, however, the data type is different.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Using the PLL in master mode requires using an external connection
between one of the GPIO pins (configured as PLL/4 output) and the
SCK pin. It also requires the external clock to be fed to some other
GPIO pin instead of the SCK pin.
This is described for the PCM5122 chip in the answers to the forum post
"PCM5122 DAC as I2S master troubles with PLL mode" at the TI E2E
community pages (1). The clocking functionality is also much better
described in the datasheet for the chip PCM5242, which seems to be
register compatible with PCM512x and PCM514x (which both have severely
lacking datasheets).
(1) http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/267830
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
Document DT binding for Qualcomm SPMI PMIC voltage ADC
driver.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
There are various issues with the examples in this documentation, some
of the DT labels are invalid and one of the macro THERMAL_NO_LIMITS
referenced is not available as well.
This patch attempts to fix such errors in the documentation.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
To support SOCs which specifies specific MMC power sequences, document
some MMC DT bindings to be able to describe these hardwares.
Let's also document bindings for a simple MMC power sequence provider,
which purpose is to support a set of common properties between various
SOCs.
In this initial step, let's also document a top level description of
the MMC power sequence and describe the compatible string used for the
simple MMC power sequence provider.
The simple MMC power sequence provider will initially support a reset
GPIO. From several earlier posted patches, it's clear that such
hardware exists. Especially some WLAN chips which are attached to an
SDIO interface may use a GPIO reset.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
The Shanghai AVIC Optoelectronics TM070DDH03 is a 7" 1024x600 TFT LCD
panel connecting to a 24-bit RGB LVDS interface.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Shanghai AVIC Optoelectronics Co., Ltd. is a subsidiary of Tianma
Microelectronics Co., Ltd. and designs and manufactures TFT LCDs.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch adds support for the GiantPlus GPG48273QS5 4.3" WQVGA TFT LCD
panel to the simple-panel driver.
This panel is connected via a parallel bus and uses both HSYNC and
VSYNC, whose lengths are unfortunately not clearly defined. The
datasheet only specifies the front- and backporch length, but the timing
diagram suggests that both sync signals should be asserted for exactly
one clock cycle.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Conflicts:
arch/arm/boot/dts/imx6sx-sdb.dts
net/sched/cls_bpf.c
Two simple sets of overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Allwinner clock changes for 3.20
The set of clock changes for the 3.20 merge window, with mostly:
- Some PLL fixes for the A80 and A31
- The MMC custom phase functions are removed, and moved over to the generic
phase API.
- Add the A80 MMC clocks
Some DT changes slipped here as well, to preserve bisectability.
Merge "ARM: rockchip: second batch of dts updates for 3.20" from Heiko Stübner:
Basic display nodes for crtcs and hdmi encoder, timer node
for the broadcast timer going through the clocksource tree
and two new boards, the rk3288-based Firefly and the
PX2-based Rayeager board (the PX2 is identical to the rk3066
but made for industrial users).
* tag 'v3.20-rockchip-dts2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add dts for ChipSPARK Rayeager PX2 board
ARM: dts: rockchip: add dts for Firefly Firefly-RK3288 boards
dt-bindings: add vendor prefix and root compatible property for Rockchip boards
ARM: dts: rockchip: Add rockchip timer node for rk3288
ARM: dts: rockchip: add rk3288 hdmi nodes
ARM: dts: rockchip: Add rk3288 vop and display-subsystem
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: mediatek: arm64 changes for v3.20" from Matthias Brugger:
Add support for mt8173 SoC from Mediatek.
- add DT bindings documentation
- add dts files for SoC and evaluation board
- add to Kconfig and defconfig
* tag 'v3.20-next-arm64' of https://github.com/mbgg/linux-mediatek:
arm64: mediatek: Add MT8173 SoC Kconfig and defconfig
arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile
Document: DT: Add bindings for mediatek MT8173 SoC Platform
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds a devicetree binding documentation for FSL's
Management Complex.
Management Complex is a hardware resource manager that manages
specialized hardware objects used in network-oriented packet
processing applications
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds a devicetree binding documentation for FSL's
LS2085A SoC and Simulator model.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch addss the device-tree documentation for Freescale's
NS16550 UART (also called DUART).
There is a specific errata fix required in FSL NS16550 UART
which ensures that an random interrupt storm is not observed when
a break is provided as an input to the UART.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
On st21nfca, the mechanism to enable a secure element needs to add 2
properties in order manage the SWP line correctly.
Document ese-present and uicc-present properties.
Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Of the Digicolor SoCs series only CX92755 is currently supported.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Olof Johansson <olof@lixom.net>
CM3232 is an advanced ambient light sensor with I2C protocol interface.
The I2C slave address is internally hardwired as 0x10 (7-bit). Writing
to configure register is byte mode, but reading ALS register requests to
use word mode for 16-bit resolution.
Signed-off-by: Kevin Tsai <ktsai@capellamicro.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
make the sta32x driver usable with device tree configs. Code is heavily based
on the sta350 driver.
Signed-off-by: Thomas Niederprüm <niederp@physik.uni-kl.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
This is needed in order to get the media fixes applied on -rc6.
Linux 3.19-rc6
* tag 'v3.19-rc6': (891 commits)
Linux 3.19-rc6
dm: fix handling of multiple internal suspends
hwmon: (i5500_temp) Convert to use ATTRIBUTE_GROUPS macro
hwmon: (i5500_temp) Convert to module_pci_driver
hwmon: (i5500_temp) Don't bind to disabled sensors
hwmon: (i5500_temp) Convert to devm_hwmon_device_register_with_groups
hwmon: (i5500_temp) New driver for the Intel 5500/5520/X58 chipsets
arm64: dts: add baud rate to Juno stdout-path
Revert "platform: x86: dell-laptop: Add support for keyboard backlight"
Revert "Documentation: Add entry for dell-laptop sysfs interface"
dm cache: fix problematic dual use of a single migration count variable
dm cache: share cache-metadata object across inactive and active DM tables
of/unittest: Overlays with sub-devices tests
KVM: x86: SYSENTER emulation is broken
KVM: x86: Fix of previously incomplete fix for CVE-2014-8480
arm64: dump: Fix implicit inclusion of definition for PCI_IOBASE
x86/tsc: Change Fast TSC calibration failed from error to info
x86/apic: Re-enable PCI_MSI support for non-SMP X86_32
x86, mm: Change cachemode exports to non-gpl
x86, tls: Interpret an all-zero struct user_desc as "no segment"
...
Conflicts:
drivers/media/pci/cx23885/cx23885.h
The Allwinner A31 SoC (sun6i) has the same resistive touchpanel controller
as on other sunxi platforms. The only difference between the variants is
the control bits for enabling operations are left-shifted by 1 on the A31.
Also update the comment for the original temperature sensor with
information from Allwinner.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
This driver implements support for PS2 controller found on Allwinner A10,
A20 SOCs. It has been tested on A20 Olimex-Lime2 board and also on A10.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
