Kevin Cernekee
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ea31a6b203
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MIPS: Honor L2 bypass bit
On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates
that the L2 cache is disabled and therefore Linux should not attempt
to use it.
[Ralf: Moved the code added by Kevin's original patch into a separate
function that can easily be replaced for platforms that need more a
different probe.]
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org>
Cc: <linux-kernel@vger.kernel.org>
Patchwork: https://patchwork.linux-mips.org/patch/1723/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2010-10-29 19:08:52 +01:00 |
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Kevin Cernekee
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96983ffefc
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MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.
This extends commit a8ca8b64e3 to cover
MIPSxx-style board cache code.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2009-09-30 21:47:00 +02:00 |
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Ralf Baechle
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234fcd1484
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[MIPS] Fix loads of section missmatches
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2008-03-12 14:14:41 +00:00 |
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Ralf Baechle
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49a89efbbb
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[MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2007-10-11 23:46:15 +01:00 |
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Atsushi Nemoto
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a2c2bc4b26
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[MIPS] MIPS32/MIPS64 S-cache fix and cleanup
Use blast_scache_range, blast_inv_scache_range for mips32/mips64 scache
routine. Also initialize waybit for MIPS32/MIPS64 S-cache.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2006-06-29 21:10:54 +01:00 |
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Chris Dearman
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9318c51acd
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[MIPS] MIPS32/MIPS64 secondary cache management
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2006-06-29 21:10:52 +01:00 |
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