Commit Graph

129978 Commits

Author SHA1 Message Date
Yendapally Reddy Dhananjaya Reddy
5072ed1fa2 arm64: dts: Add PWM DT node for NS2
Add device tree entry for PWM support for Broadcom Northstar 2 SoC.

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-08-08 11:03:58 -07:00
Hans de Goede
fbd073102c ARM: dts: sun8i: Add ethernet1 alias to Orange Pi 2 dts
This will allow u-boot to fill in a mac-address for Orange Pi 2
variants which use an sdio wifi without an eeprom for the mac.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08 20:03:51 +02:00
Hans de Goede
97c6d82b0f ARM: dts: sun8i: Add dts file for the Orange Pi PC Plus SBC
There is a new Orange Pi PC *Plus* version available now,
this is an extended version of the regular Orange Pi PC
with sdio wifi and an eMMC.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[Maxime: Fix model and compatible]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08 20:03:51 +02:00
Hans de Goede
1ff4023aab ARM: dts: sun6i-a31s-colorfly-e708-q1: Add full otg support
Now that we've all the necessary bits in place we can enable
full otg support on these tablets.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08 20:03:51 +02:00
Ville Syrjälä
65ea11ec6a x86/hweight: Don't clobber %rdi
The caller expects %rdi to remain intact, push+pop it make that happen.

Fixes the following kind of explosions on my core2duo machine when
trying to reboot or shut down:

  general protection fault: 0000 [#1] PREEMPT SMP
  Modules linked in: i915 i2c_algo_bit drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm netconsole configfs binfmt_misc iTCO_wdt psmouse pcspkr snd_hda_codec_idt e100 coretemp hwmon snd_hda_codec_generic i2c_i801 mii i2c_smbus lpc_ich mfd_core snd_hda_intel uhci_hcd snd_hda_codec snd_hwdep snd_hda_core ehci_pci 8250 ehci_hcd snd_pcm 8250_base usbcore evdev serial_core usb_common parport_pc parport snd_timer snd soundcore
  CPU: 0 PID: 3070 Comm: reboot Not tainted 4.8.0-rc1-perf-dirty #69
  Hardware name:                  /D946GZIS, BIOS TS94610J.86A.0087.2007.1107.1049 11/07/2007
  task: ffff88012a0b4080 task.stack: ffff880123850000
  RIP: 0010:[<ffffffff81003c92>]  [<ffffffff81003c92>] x86_perf_event_update+0x52/0xc0
  RSP: 0018:ffff880123853b60  EFLAGS: 00010087
  RAX: 0000000000000001 RBX: ffff88012fc0a3c0 RCX: 000000000000001e
  RDX: 0000000000000000 RSI: 0000000040000000 RDI: ffff88012b014800
  RBP: ffff880123853b88 R08: ffffffffffffffff R09: 0000000000000000
  R10: ffffea0004a012c0 R11: ffffea0004acedc0 R12: ffffffff80000001
  R13: ffff88012b0149c0 R14: ffff88012b014800 R15: 0000000000000018
  FS:  00007f8b155cd700(0000) GS:ffff88012fc00000(0000) knlGS:0000000000000000
  CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
  CR2: 00007f8b155f5000 CR3: 000000012a2d7000 CR4: 00000000000006f0
  Stack:
   ffff88012fc0a3c0 ffff88012b014800 0000000000000004 0000000000000001
   ffff88012fc1b750 ffff880123853bb0 ffffffff81003d59 ffff88012b014800
   ffff88012fc0a3c0 ffff88012b014800 ffff880123853bd8 ffffffff81003e13
  Call Trace:
   [<ffffffff81003d59>] x86_pmu_stop+0x59/0xd0
   [<ffffffff81003e13>] x86_pmu_del+0x43/0x140
   [<ffffffff8111705d>] event_sched_out.isra.105+0xbd/0x260
   [<ffffffff8111738d>] __perf_remove_from_context+0x2d/0xb0
   [<ffffffff8111745d>] __perf_event_exit_context+0x4d/0x70
   [<ffffffff810c8826>] generic_exec_single+0xb6/0x140
   [<ffffffff81117410>] ? __perf_remove_from_context+0xb0/0xb0
   [<ffffffff81117410>] ? __perf_remove_from_context+0xb0/0xb0
   [<ffffffff810c898f>] smp_call_function_single+0xdf/0x140
   [<ffffffff81113d27>] perf_event_exit_cpu_context+0x87/0xc0
   [<ffffffff81113d73>] perf_reboot+0x13/0x40
   [<ffffffff8107578a>] notifier_call_chain+0x4a/0x70
   [<ffffffff81075ad7>] __blocking_notifier_call_chain+0x47/0x60
   [<ffffffff81075b06>] blocking_notifier_call_chain+0x16/0x20
   [<ffffffff81076a1d>] kernel_restart_prepare+0x1d/0x40
   [<ffffffff81076ae2>] kernel_restart+0x12/0x60
   [<ffffffff81076d56>] SYSC_reboot+0xf6/0x1b0
   [<ffffffff811a823c>] ? mntput_no_expire+0x2c/0x1b0
   [<ffffffff811a83e4>] ? mntput+0x24/0x40
   [<ffffffff811894fc>] ? __fput+0x16c/0x1e0
   [<ffffffff811895ae>] ? ____fput+0xe/0x10
   [<ffffffff81072fc3>] ? task_work_run+0x83/0xa0
   [<ffffffff81001623>] ? exit_to_usermode_loop+0x53/0xc0
   [<ffffffff8100105a>] ? trace_hardirqs_on_thunk+0x1a/0x1c
   [<ffffffff81076e6e>] SyS_reboot+0xe/0x10
   [<ffffffff814c4ba5>] entry_SYSCALL_64_fastpath+0x18/0xa3
  Code: 7c 4c 8d af c0 01 00 00 49 89 fe eb 10 48 09 c2 4c 89 e0 49 0f b1 55 00 4c 39 e0 74 35 4d 8b a6 c0 01 00 00 41 8b 8e 60 01 00 00 <0f> 33 8b 35 6e 02 8c 00 48 c1 e2 20 85 f6 7e d2 48 89 d3 89 cf
  RIP  [<ffffffff81003c92>] x86_perf_event_update+0x52/0xc0
   RSP <ffff880123853b60>
  ---[ end trace 7ec95181faf211be ]---
  note: reboot[3070] exited with preempt_count 2

Cc: Borislav Petkov <bp@suse.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@kernel.org>
Fixes: f5967101e9 ("x86/hweight: Get rid of the special calling convention")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-08-08 10:58:25 -07:00
Thomas Petazzoni
ec03445c9e arm64: dts: marvell: add description for the Armada 8040 dev board
This commit adds a Device Tree description for the Marvell Armada 8040
Development Board. It features a quad-core Cortex A72 Armada 8040 SoC,
with a large number of peripherals: dual Gigabit, dual 10 GBit, 6 PCIe
interfaces, 6 SATA ports, 4 USB 3.0 ports, and more.

Only a subset of the functionalities are supported so far, and
additional features will be progressively enabled in the future.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 17:40:09 +02:00
Thomas Petazzoni
4eef78a009 arm64: dts: marvell: add description for the slave CP110 in Armada 8K
The Armada 8K platforms (8020 and 8040) have two CP110 HW blocks: one
master, one slave. So far, only the master CP110 was described. This
commit adds the Device Tree description for the slave CP110, and hooks
it up in the DT description of the Armada 8020 and Armada 8040 SoCs.

The slave CP110 description is somewhat similar to the master CP110
description except for a number of things like register offsets,
interrupt numbers, references to clocks, etc.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 17:40:03 +02:00
Thomas Petazzoni
d1cc3d9213 arm64: defconfig: enable xhci-platform
Some ARM64 platforms (for example the Marvell Armada 7K/8K) use the
generic XHCI platform driver, so it makes sense to enable
CONFIG_USB_XHCI_PLATFORM=y in the defconfig to support XHCI on such
platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-08-08 17:26:58 +02:00
Grzegorz Jaszczyk
c4f83aae83 ARM: mvebu: enable UBI and UBIFS in mvebu_v7_defconfig
UBIFS is commonly used on Marvell EBU v7 platforms to store the root
file-system, so it makes sense to have those options enabled by default
in mvebu_v7_defconfig.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:57:24 +02:00
Grzegorz Jaszczyk
862d56398d ARM: mvebu: enable MTD command line partition table in mvebu_v7_defconfig
Marvell EBU v7 platforms contain various MTD devices, therefore it makes
sense to allow configuring the MTD partition tables via the kernel command
line.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:57:19 +02:00
Grzegorz Jaszczyk
3566451235 ARM: dts: mvebu: armada-395-gp: add support for the Armada 395 GP Board
This commit adds description for the following features for this board:

- Serial port
- PCIe interfaces
- USB2.0
- USB3.0
- SDIO
- 1024 MiB NAND-FLASH
- SATA
- I2C buses

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:36:48 +02:00
Grzegorz Jaszczyk
0c2123a69e ARM: dts: mvebu: armada-390-db: add support for the Armada 390 DB board
This commit adds description for following features for this board:

- Serial port
- I2C buses
- 16MB SPI-NOR
- USB2.0
- USB3.0
- PCIe interfaces

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:36:27 +02:00
Grzegorz Jaszczyk
dacf5f5465 ARM: dts: mvebu: armada-398-db: enable supported usb interfaces
The Marvell Armada 398 Development board contains both USB2.0 and USB3.0
ports, which can be handled by existing drivers.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:36:24 +02:00
Grzegorz Jaszczyk
d2dd856e8c ARM: dts: mvebu: armada-398: update the dtsi about missing interfaces
Beside interfaces described in the armada-39x.dtsi and armada-395.dtsi, the
Armada 398 SoC family supports 2 additional SATA port (2 ports in one unit)

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:36:18 +02:00
Grzegorz Jaszczyk
eebead7853 ARM: dts: mvebu: armada-395: add support for the Armada 395 SoC family
Beside interfaces described in the armada-39x.dtsi, the Armada 395 SoC
family supports: 2 x SATA3 (2 ports in one unit) and the USB3.0

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:30:23 +02:00
Grzegorz Jaszczyk
daab54316b ARM: dts: mvebu: armada-39x: enable rtc for all Armada-39x SoCs
Despite that FS states that rtc is present only in A395 and A398 and not in
A390, the rtc is working with A390.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:54 +02:00
Grzegorz Jaszczyk
d81a914fc6 ARM: dts: mvebu: armada-39x: add missing nodes describing GPIO's
The whole Armada 39x SoC family of processors has GPIO's which all can be
supported with existing driver.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:54 +02:00
Grzegorz Jaszczyk
100a20a9ff ARM: dts: mvebu: armada-39x: enable watchdog for all Armada-39x SoCs
The whole Armada 39x SoC family of processors has watchdog which can be
supported with existing driver.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Lior Amsalem <alior@marvell.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:53 +02:00
Grzegorz Jaszczyk
16ae883151 ARM: dts: mvebu: armada-39x: enable the thermal sensor in Armada-39x SoCs
The whole Armada 39x SoC family of processors has thermal sensor which can
be supported with existing driver.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:53 +02:00
Grzegorz Jaszczyk
8deebf8b8a ARM: dts: mvebu: armada-39x: enable PMU, CA9 SoC Controller and Coherency fabric
This commit enables:
- CA9's Performance Monitor Unit
- CA9 MPcore SoC Controller
- Coherency fabric
on Armada 39x, basing on the Armada 38x (which has the same CA9 CPU).

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Lior Amsalem <alior@marvell.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:52 +02:00
Grzegorz Jaszczyk
39f3c23f51 ARM: dts: mvebu: armada-39x: update the SDHCI node on Armada 39x
Commit 1140011ee9 ("mmc: sdhci-pxav3: Modify clock settings
for the SDR50 and DDR50 modes") has extended the Device Tree
binding used to describe PXAv3 SDHCI controllers in order to be
able to use the SDR50 and DDR50 modes.

This commit updates the Device Tree description of the Armada
39x SDHCI controller in other to take advantage of this
functionality.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:52 +02:00
Grzegorz Jaszczyk
061492cfad ARM: dts: mvebu: armada-390: add missing compatibility string and bracket
The armada-390.dtsi was broken since the first patch which adds Device Tree
files for Armada 39x SoC was introduced.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: <stable@vger.kernel.org> # 4.0+
Fixes 538da83 ("ARM: mvebu: add Device Tree files for Armada 39x SoC and board")

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:51 +02:00
Grzegorz Jaszczyk
4ec17292a9 ARM: dts: mvebu: a385-db-ap: add default partition description for NAND
The Armada 385 Access Point Development board contains NAND FLSH which is
already enabled in existing dts. Nevertheless the default partition
description was missing.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:51 +02:00
Grzegorz Jaszczyk
b583e291ba ARM: dts: mvebu: a385-db-ap: enable USB (orion-ehci) port
The Armada 385 Access Point Development board contains USB port, which can
be handled by existing orion-ehci driver.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:28:47 +02:00
Stefan Roese
55877f58b0 ARM: dts: mvebu: armada-370-xp: Add MBus mappings for all SPI devices
This patch adds the static MBus mappings for all supported SPI devices
(8 per controller) for the direct access SPI mode. They can be configured
and enabled by setting these MBus mapping in the 'ranges' property of the
per-board 'soc' node. If nothing is changed here, the default 'normal'
(indirect) SPI mode is used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Mark Brown <broonie@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:16:44 +02:00
Stefan Roese
0160a4b689 ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node
This patch moves all Armada 370/XP/38x/39x SPI controller nodes from the
'internal-regs' node down into the 'soc' node. This is in preparation
to enable the usage of the SPI direct access mode. A follow-up patch
will add the static MBus mappings for the SPI devices into the 'reg'
property of the SPI controller DT node.

By moving these SPI controller nodes, this patch also makes use of
the labels rather than keeping the tree structure.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Mark Brown <broonie@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:16:31 +02:00
Stefan Roese
1113603e39 ARM: dts: mvebu: Add SPI1 pinctrl defines for Armada XP
This patch defines and uses common Armada XP pinctrl settings in
armada-xp.dtsi for the SPI1 interface (MPP13,14,16,17).

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 16:16:09 +02:00
Andreas Färber
b9700be51b ARM: dts: imx6sx-sabreauto: Fix misspelled property
In commit 99fc5ba0bf ("ARM: dts: imx6sx: add i.mx6sx sabreauto board
support") it should've been enable-sdio-wakeup (not -wakup). But that is
now considered a legacy name for wakeup-source, so directly use the new
name instead, as done in commit 26cefdd15d for the other occurrence.

Fixes: 26cefdd15d ("ARM: dts: imx: replace legacy wakeup property with 'wakeup-source'")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-08 21:57:37 +08:00
Christian Borntraeger
6e127efeea s390/config: make the vector optimized crc function builtin
For all configs with CONFIG_BTRFS_FS = y we should also make the
optimized crc module builtin. Otherwise early mounts will fall
back to the software variant.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-08-08 15:41:32 +02:00
Christian Borntraeger
e2efc42454 s390/lib: fix memcmp and strstr
if two string compare equal the clcle instruction will update the
string addresses to point _after_ the string. This might already
be on a different page, so we should not use these pointer to
calculate the difference as in that case the calculation of the
difference can cause oopses.

The return value of memcmp does not need the difference, we
can just reuse the condition code and return for CC=1 (All bytes
compared, first operand low) -1 and for CC=2 (All bytes compared,
first operand high) +1
strstr also does not need the diff.
While fixing this, make the common function clcle "correct on its
own" by using l1 instead of l2 for the first length. strstr will
call this with l2 for both strings.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Fixes: db7f5eef3d ("s390/lib: use basic blocks for inline assemblies")
Reviewed-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-08-08 15:41:31 +02:00
Christian Borntraeger
134a24cd89 s390/crc32-vx: Fix checksum calculation for small sizes
The current prealign logic will fail for sizes < alignment,
as the new datalen passed to the vector function is smaller
than zero. Being a size_t this gets wrapped to a huge
number causing memory overruns and wrong data.

Let's add an early exit if the size is smaller than the minimal
size with alignment. This will also avoid calling the software
fallback twice for all sizes smaller than the minimum size
(prealign + remaining)

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Fixes: f848dbd3bc ("s390/crc32-vx: add crypto API module for optimized CRC-32 algorithms")
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-08-08 15:41:31 +02:00
Sascha Silbe
bf47dc572a s390: clarify compressed image code path
The way the decompressor is hooked into the start-up code is rather
subtle, with a mix of multiply-defined symbols and hardcoded address
literals. Add some comments at the junction points to clarify how it
works.

Signed-off-by: Sascha Silbe <silbe@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-08-08 15:41:31 +02:00
Alexander Kurz
d7b5ccc9fc ARM: i.MX31 iomux: remove duplicates with alternate name
Three iomux were accessinble with two distinct names, typo?
Remove the unused duplicates and fix the typo.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-08 21:41:17 +08:00
Alexander Kurz
dd19e828ce ARM: i.MX31 iomux: remove plain duplicates
No need to define some of the iomux twice, remove the duplicates.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-08 21:40:45 +08:00
Russell King
d9fd3c9181 ARM: dts: armada-388-clearfog: number LAN ports properly
Currently, the ports as seen from the rear number as:

	eth0 sfp lan5 lan4 lan3 lan2 lan1 lan6

which is illogical - this came about because the rev 2.0 boards have the
LEDs on the front for the DSA switch (lan5-1) reversed.  Rev 2.1 boards
fixed the LED issue, and the Clearfog case numbers the lan ports
increasing from left to right.

Maintaining this illogical numbering causes confusion, with reports that
"my link isn't coming up" and "my connection negotiates 10base-Half"
both of which are due to people thinking that the port next to the SFP
is lan1.

Fix this by renumbering the ports to match people's expectations.

[gregory.clement@free-electrons.com: added the Fixes and stable tags]

Fixes: 4c945e8556 ("ARM: dts: Add SolidRun Armada 388 Clearfog A1 DT
file")
Cc: <stable@vger.kernel.org>

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-08 13:20:24 +02:00
Sylwester Nawrocki
11496471a1 ARM: S3C24XX: Specify audio codec platform_data for mini2440 board
The L3 bus GPIOs are specified in the board file rather than through
the sound card's device platform_data. This allows to ensure the codec
driver doesn't get probed with uninitialized platform_data field of
its corresponding platform device.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-08 11:55:20 +01:00
Kevin Hilman
97608f5cce ARM: davinci_all_defconfig: enable DA850 audio as modules
Build audio support for DA850-based devices as modules in the default
defconfig.

Cc: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-08-08 16:24:56 +05:30
Kevin Hilman
8134fb1b85 ARM: davinci_all_defconfig: cleanup with savedefconfig
It's been awhile since a cleanup was done.  Regenerate the default settings by

$ make davinci_all_config
$ make savedefconfig
$ cp defconfig arch/arm/configs/davinci_all_defconfig

Cc: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-08-08 16:24:56 +05:30
Simon Horman
83701e00de ARM: dts: r8a7794: Correct SDHI register size
r8a7794 SDHI ch0 has SD_DMACR which is located in 0x324.
This patch updates register size

Based on work for the r8a7790 by Kuninori Morimoto.

Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2016-08-08 12:53:06 +02:00
Sergei Shtylyov
38584104ea ARM: dts: blanche: add CAN0 support
Define the Blanche board dependent part of the CAN0 device node along with
the CAN_CLK crystal.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:53:04 +02:00
Sergei Shtylyov
f947c02a0f ARM: dts: r8a7792: add CAN support
Define the generic R8A7792 parts of the CAN0/1 device nodes.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:53:02 +02:00
Sergei Shtylyov
47db051c22 ARM: dts: r8a7792: add CAN clocks
The R-Car CAN controllers can derive  the CAN  bus  clock not only from
their peripheral  clock input (clkp1) but also from the other internal
clock (clkp2) and the external clock fed on the CAN_CLK pin.  Describe
those  clocks in  the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:53:00 +02:00
Sergei Shtylyov
b12dcdcc47 ARM: dts: r8a7792: add EtherAVB support
Define the generic R8A7792 part of the EtherAVB device node.

Based on the commit 89aac8af1a ("ARM: dts: r8a7794: add EtherAVB support").

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:52:58 +02:00
Sergei Shtylyov
08cafff67e ARM: dts: r8a7792: add EtherAVB clocks
Add the EtherAVB clock and its parent, HP clock to the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:52:56 +02:00
Sergei Shtylyov
63359c2ddc ARM: dts: r8a7792: add GPIO support
Describe all 12 GPIO controllers in the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:52:54 +02:00
Sergei Shtylyov
4e2b4f6626 ARM: dts: r8a7792: add GPIO clocks
Describe the GPIO clocks in the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:52:52 +02:00
Sergei Shtylyov
1d93a8b5a2 ARM: dts: blanche: add Ethernet pins
Add the (previously omitted) pin data for the SMSC LAN89218 Ethernet chip
to  the Blanche board's device tree:  the chip's IRQ output is connected to
the SoC's IRQ0 pin and its nCS input is connected to the SoC's EX_CS0# pin.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:52:50 +02:00
Sergei Shtylyov
2cd452d19e ARM: dts: blanche: add SCIF0/3 pins
Add the (previously omitted) SCIF0/3 pin data to the Blanche board's
device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:52:48 +02:00
Sergei Shtylyov
02183a5250 ARM: dts: r8a7792: add PFC support
Define the generic R8A7792 part of the PFC device node.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08 12:52:46 +02:00
Olivier Schonken
e46f48ad86 ARM: dts: at91: sama5d2: add ETM and ETB nodes
Add node to support SAMA5D2 Embedded Trace Macrocell and Embedded
Trace Buffer.

This patch depends on coresight-etm3x: Add ARM ETM-A5 peripheral ID
for proper coresight functionality.
It also depends on clocksource: timer-atmel-pit: enable mck to not
stall SAMA5D2 on bootup.

Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-08-08 12:08:00 +02:00