MIN_HUGEPTE_SHIFT hasn't been used since commit d1837cba5d
("powerpc/mm: Cleanup initialization of hugepages on powerpc")
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
UART3 device is not really needed for enabling audio block on TM2.
Enabling it made it working by enabling some common parent clocks,
what is now handled by improved exynos5433 clocks driver. Thus the UART3
device node can be safely disabled. The assigned-clocks entries are
however still needed, so move them under the respective CMU node.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
a board specific item.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Audio PLL and oscillator clocks are proper parent clocks for AUD CMU.
They are not visible as such on first glance on Exynos5433 SoC docs,
but they are needed for this CMU to operate properly.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch corrects FSYS CMU parent clocks specified in clock controller
node to let improved Exynos5433 clocks driver to control proper clocks
on FSYS<->TOP CMU boundary.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts. The
GIC requires shared interrupts to be edge rising or level high. Platform
declares support for both. Set all interrupts type to level high, as this
works fine - tested on Exynos5433-based TM2 board.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
All places which used the TSC_RELIABLE to skip the delayed calibration
have been converted to use the TSC_KNOWN_FREQ flag.
Make the immeditate clocksource registration, which skips the long term
calibration, solely depend on TSC_KNOWN_FREQ.
The TSC_RELIABLE now merily removes the requirement for a watchdog
clocksource.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
reliable and the frequency is known (provided by HW).
On these platforms PIT/HPET is generally not available so calibration won't
work at all and there is no other clocksource to act as a watchdog for the
TSC, so we have no other choice than to trust it.
Set both X86_FEATURE_TSC_KNOWN_FREQ and X86_FEATURE_TSC_RELIABLE flags to
make sure the calibration is skipped and no watchdog is required.
Signed-off-by: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-5-git-send-email-bin.gao@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
On Intel GOLDMONT Atom SoC TSC is the only available clocksource, so there
is no way to do software calibration or have a watchdog clocksource for it.
Software calibration is already disabled via the TSC_KNOWN_FREQ flag, but
the watchdog requirement still persists, so such systems cannot switch to
high resolution/nohz mode.
Mark it reliable, so it becomes usable. Hardware teams confirmed that this
is safe on that SoC.
Signed-off-by: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-4-git-send-email-bin.gao@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
CPUs/SoCs with CPUID leaf 0x15 come with a known frequency and will report
the frequency to software via CPUID instruction. This hardware provided
frequency is the "real" frequency of TSC.
Set the X86_FEATURE_TSC_KNOWN_FREQ flag for such systems to skip the
software calibration process.
A 24 hours test on one of the CPUID 0x15 capable platforms was
conducted. PIT calibrated frequency resulted in more than 3 seconds drift
whereas the CPUID determined frequency showed less than 0.5 second
drift.
Signed-off-by: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-3-git-send-email-bin.gao@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The X86_FEATURE_TSC_RELIABLE flag in Linux kernel implies both reliable
(at runtime) and trustable (at calibration). But reliable running and
trustable calibration independent of each other.
Add a new flag X86_FEATURE_TSC_KNOWN_FREQ, which denotes that the frequency
is known (via MSR/CPUID). This flag is only meant to skip the long term
calibration on systems which have a known frequency.
Add X86_FEATURE_TSC_KNOWN_FREQ to the skip the delayed calibration and
leave X86_FEATURE_TSC_RELIABLE in place.
After converting the existing users of X86_FEATURE_TSC_RELIABLE to use
either both flags or just X86_FEATURE_TSC_KNOWN_FREQ we can seperate the
functionality.
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-2-git-send-email-bin.gao@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
KVM calls kvm_pmu_set_counter_event_type() when PMCCFILTR is configured.
But this function can't deals with PMCCFILTR correctly because the evtCount
bits of PMCCFILTR, which is reserved 0, conflits with the SW_INCR event
type of other PMXEVTYPER<n> registers. To fix it, when eventsel == 0, this
function shouldn't return immediately; instead it needs to check further
if select_idx is ARMV8_PMU_CYCLE_IDX.
Another issue is that KVM shouldn't copy the eventsel bits of PMCCFILTER
blindly to attr.config. Instead it ought to convert the request to the
"cpu cycle" event type (i.e. 0x11).
To support this patch and to prevent duplicated definitions, a limited
set of ARMv8 perf event types were relocated from perf_event.c to
asm/perf_event.h.
Cc: stable@vger.kernel.org # 4.6+
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Wei Huang <wei@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We're missing the handling code for the cycle counter accessed
from a 32bit guest, leading to unexpected results.
Cc: stable@vger.kernel.org # 4.6+
Signed-off-by: Wei Huang <wei@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
- clean up mach-mediatek Makefile as kbuild only descends into the folder if
ARCH_MEDIATEK is enabled
* tag 'v4.9-next-kconfig' of https://github.com/mbgg/linux-mediatek:
ARM: mediatek: clean up mach-mediatek/Makefile
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add bindings for mtk-scpsys for mt2701
- Add clocks for auxadc on mt8173-evb
- Add nodes needed by clock controller for mt2701
- Use clocks from the clock controller for the uart of mt2701
* tag 'v4.9-next-dts' of https://github.com/mbgg/linux-mediatek:
arm: dts: mt2701: Use real clock for UARTs
arm: dts: mt2701: Add clock controller device nodes
arm64: dts: mt8173: Fix auxadc node
soc: mediatek: Add MT2701 power dt-bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
Qualcomm ARM Based SoC Updates for v4.10
* Enable GPIOLIB for QCOM ARM64 platforms
* tag 'qcom-soc-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: qcom: enable GPIOLIB in Kconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
Qualcomm ARM Based defconfig Updates for v4.10
* Fixup MDM9615 option names
* tag 'qcom-defconfig-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config
Signed-off-by: Olof Johansson <olof@lixom.net>
Qualcomm ARM64 Based defconfig Updates for v4.10
* Enable defconfig options for MSM8992/8994
* tag 'qcom-arm64-defconfig-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: configs: enable configs for msm899(2/4) basic support
Signed-off-by: Olof Johansson <olof@lixom.net>
64bit devicetree changes including the px5 evaluation board
a fix for wrong i2c registers on rk3368 a new nvmem cell and
power-domain on rk3399 as well as moving mmc frequency
properties to the more generic max-frequency one.
* tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399
arm64: dts: rockchip: add sdmmc support for px5-evb
arm64: dts: rockchip: Add more properties for emmc on px5-evb
arm64: dts: rockchip: Add PX5 Evaluation board
arm64: dts: rockchip: add powerdomain for typec on rk3399
arm64: dts: rockchip: fix i2c resource error of rk3368
Signed-off-by: Olof Johansson <olof@lixom.net>
32bit devicetree changes for Rockchip including removal of skeleton.dtsi
inclusion, missing unit names for memory nodes, various frequency
optimizations allowing for better performance on rk3066, the usage of
pin constants to bridge between the two numbering schemes used (gpio
controllers using 0-31 and pins being labeled A0-A7,..., D0-D7)
and UHS/HS modes for the mmc controllers on the popmetal board.
Two new boards, the PX3-based evaluation board, with the PX3 being an
industrial variant of the rk3188 soc and the Rikomagic MK808 board
based around the rk3066 are also added.
* tag 'v4.10-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits)
ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
ARM: dts: rockchip: Set sdmmc frequency at boot time for rk3066a
ARM: dts: rockchip: use pin constants to describe gpios on Popmetal-RK3288
include: dt-bindings: Add GPIO pin index definition for rockchip pinctrl
ARM: dts: rockchip: Add rk3066 MK808 board
devicetree: Add vendor prefix for Rikomagic
ARM: dts: rockchip: initialize rk3066 PLL clock rate
clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
ARM: dts: rockchip: enable HS200/DDR52 mode for emmc on rk3288-popmetal
ARM: dts: rockchip: Support UHS mode for SD card on PopMetal-RK3288 board
ARM: dts: rockchip: remove always-on and boot-on from vcc_sd for px3-evb
ARM: dts: rockchip: update compatible strings for Rockchip efuse
ARM: dts: rockchip: add rockchip PX3 Evaluation board
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3036 boards
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3xxx.dtsi
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3288.dtsi
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk322x.dtsi
...
Signed-off-by: Olof Johansson <olof@lixom.net>
SoCFPGA defconfig updates for v4.10
- enable QSPI, HIGHMEM, FPGA bridge and device-tree overlays
- enable AUTOFS4 and NFS file system support
* tag 'socfpga_defconfig_updates_for_v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: socfpga_defconfig: enable FS configs to support Angstrom filesystem
ARM: socfpga: updates for socfpga_defconfig
ARM: socfpga_defconfig: Enable HIGHMEM
ARM: socfpga: defconfig: enable qspi
Signed-off-by: Olof Johansson <olof@lixom.net>
SoCFPGA DTS update for v4.10, part 2
- Add specific compatible strings for variants of Cyclone5 boards
- Add QSPI node on Arria10
- Enable QSPI on Arria5 and Arria10 devkit, and Cyclone5 SoCKit
- Add NAND controller node on Cyclone5
* tag 'socfpga_dts_for_v4.10_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: add nand controller nodes
ARM: dts: socfpga: Enable QSPI on the Arria5 devkit
ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit
ARM: dts: socfpga: Enable QSPI in Arria10 devkit
ARM: dts: socfpga: Add QSPI node for the Arria10
ARM: dts: socfpga: enable qspi on the Cyclone5 devkit
ARM: dts: socfpga: add specific compatible strings for boards
Signed-off-by: Olof Johansson <olof@lixom.net>
* 'sti-defconfig-for-4.10-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
ARM: multi_v7_defconfig: Remove ST_THERMAL_SYSCFG Kconfig symbol
Signed-off-by: Olof Johansson <olof@lixom.net>
The EBI lookup is not longer in use: this has been moved to the
NAND chip driver. The syscon node is better accessed indirectly
using the regmap like the NAND chip driver does, so let's use
the syscon to set the modem control signals RTS/CTS through the
dedicated syscon register.
We also migrate the decoder status "SC_DEC" register that
enumerate the logic modules using syscon.
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This is the pxa changes for v4.10 cycle.
This cycle is covering :
- some clock fixes common with sa1100 architecture
- the consequence of the pxa_camera conversion to v4l2
- a small irq related fix for pxa25x device-tree only
* tag 'pxa-for-4.10' of https://github.com/rjarzmik/linux:
ARM: pxa: fix pxa25x interrupt init
ARM: pxa: remove duplicated include from spitz.c
ARM: pxa: em-x270: use the new pxa_camera platform_data
ARM: pxa: ezx: use the new pxa_camera platform_data
ARM: pxa: mioa701: use the new pxa_camera platform_data
ARM: pxa: pxa_cplds: honor probe deferral
ARM: sa11x0/pxa: get rid of get_clock_tick_rate
watchdog: sa11x0/pxa: get rid of get_clock_tick_rate
ARM: sa11x0/pxa: acquire timer rate from the clock rate
clk: pxa25x: OSTIMER0 clocks from the main oscillator
Signed-off-by: Olof Johansson <olof@lixom.net>
On POWER9 DD1, when we do a local TLB invalidate we also need to explicitly
invalidate the ERAT.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Finally, I am really pleased to announce adding support for Exynos5433 ARMv8
SoC along with two boards. A lot of Samsung people contributed into this
but the final work and commits were done by Chanwoo Choi.
This means that for v4.10 we got:
1. Exynos5433 DTSI.
2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones.
* tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board
arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
Samsung DeviceTree update for v4.10:
1. Add TOPEET itop core and Elite boards, based on Exynos4412.
2. Remove the Exynos4415 DTSI. We did not have any mainlined boards
using it. I am also not aware of any popular out-of-tree boards using it.
3. Add Snoop Control Unit node for Exynos4.
4. Minor cleanups.
* tag 'samsung-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Add SCU device node to exynos4.dtsi
ARM: dts: exynos: Remove exynos4415.dtsi
ARM: dts: exynos: Document eMMC/SD/SDIO devices in Snow and Peach boards
ARM: dts: exynos: Add TOPEET itop elite based board
ARM: dts: exynos: Add TOPEET itop core board SCP package version
ARM: dts: exynos: Add entries for sound support on Odroid-XU board
ARM: dts: exynos: Remove "simple-bus" compatible from fimc-is node
Signed-off-by: Olof Johansson <olof@lixom.net>
Samsung defconfig update for v4.10:
1. Enable the Exynos gscaler driver on multi_v7 and exynos defconfigs.
* tag 'samsung-defconfig-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: multi_v7_defconfig: Enable exynos-gsc driver as module
ARM: exynos_defconfig: Enable exynos-gsc driver as module
Signed-off-by: Olof Johansson <olof@lixom.net>
NXP LPC32xx ARM SoC device tree updates for v4.10
This includes a single functional change:
* set default parent clock for PWM1 & PWM2.
* tag 'lpc32xx-dt-v4.10' of https://github.com/sylemieux/linux-lpc32xx:
ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2
Signed-off-by: Olof Johansson <olof@lixom.net>
UniPhier ARM64 SoC DT updates for v4.10
- Switch CPU enable-method from spin-table to PSCI
- Add OPP tables to support generic cpufreq driver
- Misc fixes
* tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific
arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
arm64: dts: uniphier: increase register region size of sysctrl node
arm64: dts: uniphier: switch over to PSCI enable method
Signed-off-by: Olof Johansson <olof@lixom.net>
Linux 4.9-rc3
* tag 'v4.9-rc3': (292 commits)
Linux 4.9-rc3
x86/smpboot: Init apic mapping before usage
ACPICA: Dispatcher: Fix interpreter locking around acpi_ev_initialize_region()
ACPICA: Dispatcher: Fix an unbalanced lock exit path in acpi_ds_auto_serialize_method()
ACPICA: Dispatcher: Fix order issue of method termination
ARC: module: print pretty section names
ARC: module: elide loop to save reference to .eh_frame
ARC: mm: retire ARC_DBG_TLB_MISS_COUNT...
ARC: build: retire old toggles
ARC: boot log: refactor cpu name/release printing
ARC: boot log: remove awkward space comma from MMU line
ARC: boot log: don't assume SWAPE instruction support
ARC: boot log: refactor printing abt features not captured in BCRs
ARCv2: boot log: print IOC exists as well as enabled status
ubifs: Fix regression in ubifs_readdir()
ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap()
MAINTAINERS: Add entry for genwqe driver
VMCI: Doorbell create and destroy fixes
GenWQE: Fix bad page access during abort of resource allocation
vme: vme_get_size potentially returning incorrect value on failure
...
UniPhier ARM SoC DT updates for v4.10
- Add OPP tables to support generic cpufreq driver
- Use more clocks/resets properties
- Misc fixes and cleanups
* tag 'uniphier-dt-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
ARM: dts: uniphier: make compatible of syscon nodes SoC-specific
ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC
ARM: dts: uniphier: remove redundant serial fifo-size properties
ARM: dts: uniphier: make 32bit SoC DTSI linear
ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC
ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC
ARM: dts: uniphier: increase register region size of sysctrl node
Signed-off-by: Olof Johansson <olof@lixom.net>
Linux 4.9-rc3
* tag 'v4.9-rc3': (292 commits)
Linux 4.9-rc3
x86/smpboot: Init apic mapping before usage
ACPICA: Dispatcher: Fix interpreter locking around acpi_ev_initialize_region()
ACPICA: Dispatcher: Fix an unbalanced lock exit path in acpi_ds_auto_serialize_method()
ACPICA: Dispatcher: Fix order issue of method termination
ARC: module: print pretty section names
ARC: module: elide loop to save reference to .eh_frame
ARC: mm: retire ARC_DBG_TLB_MISS_COUNT...
ARC: build: retire old toggles
ARC: boot log: refactor cpu name/release printing
ARC: boot log: remove awkward space comma from MMU line
ARC: boot log: don't assume SWAPE instruction support
ARC: boot log: refactor printing abt features not captured in BCRs
ARCv2: boot log: print IOC exists as well as enabled status
ubifs: Fix regression in ubifs_readdir()
ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap()
MAINTAINERS: Add entry for genwqe driver
VMCI: Doorbell create and destroy fixes
GenWQE: Fix bad page access during abort of resource allocation
vme: vme_get_size potentially returning incorrect value on failure
...
STM32 DT updates for v4.10, round 1.
Highlights:
----------
- Add LSI and LSE clocks support for STM32F429
- Add GPIO IRQ support for STM32F429
- Declare push button as GPIO keys on STM32F429 boards
- Add DMA supports on USART1 & USART3 on STM32F429
- Add Ethernet fixes
* tag 'stm32-dt-for-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: dts: stm32f429: add LSI and LSE clocks
ARM: dts: stm32f429: remove Ethernet wake on Lan support
ARM: dts: stm32f429: Fix Ethernet node on Eval Board
ARM: dts: stm32f429: Align Ethernet node with new bindings properties
ARM: DT: stm32: move dma translation to board files
ARM: DT: STM32: add dma for usart3 on F429
ARM: DT: STM32: add dma for usart1 on F429
ARM: dts: Declare push button as GPIO key on stm32f429 boards
ARM: dts: Add GPIO irq support to STM32F429
Signed-off-by: Olof Johansson <olof@lixom.net>
Renesas ARM Based SoC Updates for v4.10
Enhancements:
* Basic support for r8a7743 SoC; only SoC code so far
* Select errata 798181 for SoCs with CA15 cores
Clean-up:
* Consolidate R8A7743 and R8A779[234] machine definitions
Documentation:
* Add Marzen, Gose and Alt board part numbers to DT bindings
* Document SK-RZG1M board
* tag 'renesas-soc-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7779/marzen: Add board part number to DT bindings
ARM: shmobile: select errata 798181 for SoCs with CA15 cores
ARM: shmobile: Consolidate R8A7743 and R8A779[234] machine definitions
ARM: shmobile: r8a7793/gose: Add board part number to DT bindings
ARM: shmobile: r8a7794/alt: Add board part number to DT bindings
ARM: shmobile: document SK-RZG1M board
ARM: shmobile: r8a7743: basic SoC support
ARM: shmobile: only call rcar_gen2_clocks_init() if present
ARM: shmobile: Sort Kconfig selections
Signed-off-by: Olof Johansson <olof@lixom.net>
Add blue-and-red-wiring -property to LCDC node. Also adds comments on
how to get support 24 bit RGB mode. After this patch am335x-boneblack
support RGB565, BGR888, and XBGR8888 color formats. See details in
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.
The BBB has straight color wiring from am335x to tda19988, however the
tda19988 can be configured to cross the blue and red wires. The
comments show how to do that with video-ports property of tda19988
node and how to tell LCDC that blue and red wires are crossed, with
blue-and-red-wiring LCDC node property. This changes supported color
formats from 16 bit RGB and 24 bit BGR to 16 bit BGR and 24 bit RGB.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
