Remove a redundant call to `ieee754_setandtestcx' in `ieee754sp_cmp' and
`ieee754dp_cmp'. The IEEE 754 exception requested will have already
been set by a call to `ieee754_setcx' immediately above, because `sig'
has to be non-zero to reach here, and the comparison result returned
will be 0 regardless of the result from the call. Simplify the return
expression remaining. All this reducing the size of code by 16 and 12
instructions or 64 and 48 bytes respectively.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9690/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We have the input operands already classified in `ieee754sp_cmp' and
`ieee754dp_cmp' comparison operations, so use the class obtained to tell
NaNs and numbers apart rather than classifying inputs again for this
purpose, reducing the size of code by 24 and 40 instructions or 96 and
160 bytes respectively.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9689/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Revert the changes made by commit fdffbafb [Lots of FPU bug fixes from
Kjeld Borch Egevang.] to `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt'
sNaN quieting handlers and their callers so that sNaN processing is done
within the handlers againg. Pass the sNaN causing an IEEE 754 invalid
operation exception down to the relevant handler. Pass the sNaN in `fs'
where two sNaNs are supplied to a binary operation.
Set the Invalid Operation FCSR exception bits in the quieting handlers
rather than at their call sites throughout. Make the handlers exclusive
for sNaN processing.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9688/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Don't call the `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' sNaN quieting
handlers for a qNaN supplied to floating-point format conversions or
SQRT.S/SQRT.D instructions, or for a qNaN produced out of a negative
operand supplied to SQRT.S/SQRT.D instructions. Return the qNaN right
away in these cases.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9687/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.]
replaced the two single `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt'
places, where sNaN quieting used to happen for single and double
floating-point operations respectively, with individual qNaN
instantiations across all the call sites instead. It also made most of
these two functions dead code as where called on a qNaN they return
right away.
To revert the damage and make sNaN quieting uniform again first rewrite
`ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' to do the same quieting all
the call sites do, that is return the default qNaN encoding for all
input sNaN values; never propagate any sNaN payload bits from its
trailing significand field.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9685/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Changes applied to `do_cpu' over time reduced the use of the SIGILL
issued with `force_sig' at the end to a single CU3 case only in the
switch statement there. Move that `force_sig' call over to right where
required then and toss out the pile of gotos now not needed to skip over
the call, replacing them with regular breaks out of the switch.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9683/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
GCC is smart enough to substitute the final result for FLS calculations
as implemented in the fallback C code we have in `__fls' and `fls'
applied to constant values. The presence of inline asm defeats the
compiler though, forcing it to emit extraneous CLZ/DCLZ calculation for
processors that support these instructions.
Use `__builtin_constant_p' then to avoid inline asm altogether for
constants.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9681/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit 56a64733 [MIPS: math-emu: Switch to using the MIPS rounding
modes.] removed the distinction between hardware and emulator rounding
mode encodings, the hardware encoding is now used in emulation as well.
Complement the change and remove the `modeindex' macro previously used
for indexing into encoding translation tables, it now does nothing and
only obfuscates code by reinserting the value extracted from FCSR.
Adjust comments accordingly.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9680/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
IEEE754_SPCVAL_NMIN denotes the index into the special value array where
the closest to zero negative normal number expressible is stored.
Similarly IEEE754_SPCVAL_NMIND denotes such index for the closest to
zero negative subnormal number expressible. Make comments match that.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9670/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reindent CP0 Cause macros for a single space after #define, leaving
extra indentation for individual Interrupt Pending bits as with CP0
Status register's Interrupt Mask bits.
[ralf@linux-mips.org: Fix conflict.]
[ralf@linux-mips.org: Fix indentation of the CAUSEB_FDCI and CAUSEF_FDCI
definitions.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9669/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
TX39 CP0 Configuration Register 3 macro definitions have been randomly
thrown in the middle of a block of CP0 Status register value macros.
Move them to the end of the whole CP0 register value macro block,
complementing the location of the TX39 Cache register name macro at the
end of the CP0 register name macro block.
[ralf@linux-mips.org: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Originally CP1 macros were placed between CP0 register name macros and
CP0 register value macros. As changes were applied to the header the
position of CP1 macros gradually has become more and more arbitrary and
two separate blocks were created. This may only cause confusion.
Move them out of the way then and place together after all the CP0
macros. No semantic change.
[ralf@linux-mips.org: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9667/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Remove a duplicate FPU Status Register reference that has been there
since forever and a mistakenly copied and pasted R4xx0 manual reference.
[ralf@linux-mips.org: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This cleanup is prepare to move the driver to drivers/gpio. Custom
definitions of gpio_get_value()/gpio_set_value() are dropped.
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As part of addressing in-kernel y2038 issues, this patch adds
read_persistent_clock64() and replaces all the call sites of
read_persistent_clock() with this function. This is a __weak
implementation, which simply calls the existing y2038 unsafe
read_persistent_clock().
This allows architecture specific implementations to be
converted independently, and eventually the y2038 unsafe
read_persistent_clock() can be removed after all its
architecture specific implementations have been converted to
read_persistent_clock64().
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Xunlei Pang <pang.xunlei@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1427945681-29972-3-git-send-email-john.stultz@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Prior to this commit, it was impossible to use relative path to
include Makefiles from the top level Makefile because the option
"--include-dir=$(srctree)" becomes effective when Make enters into
sub Makefiles.
To use relative path in any places, this commit moves the option
above the "sub-make" target.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.cz>
So let's remove everythig that only make sense for a kernel module and
build the thing unconditionally.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This simplifies code a lot by dropping many per-revision-group
functions. There are still some paths left that use uncommon NVRAM read
helpers or fill arrays. They will need to be handled in separated patch.
I've tested this (by printing SPROM content) for regressions on:
1) BCM4704 (SPROM revision 2)
2) BCM4706 (SPROM revision 8 plus 11 & 9 on extra WiFi cards)
The only difference is not reading board_type from SPROM rev 11 which is
unsupported and treated as rev 1. This change for rev 1 is expected.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9660/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Handling many SPROM revisions became messy, we have tons of functions
specific to various revision groups which are quite hard to track.
For years there is yet another revision 11 asking for support, but
adding it in current the form would make things even worse.
To resolve this problem let's add new function with table-like entries
that will contain revision bitmask for every SPROM variable.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9659/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
!CONFIG_DEBUG_ZBOOT doesn't need puts() and puthex(), remove them and
the corrospindig strings for !CONFIG_DEBUG_ZBOOT, as a result, it saves
about 1280 bytes.
[ralf@linux-mips.org: Resolved reject.]
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Wu Zhangjin <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/1898/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fix the 74K D-cache alias erratum workaround so that it actually works.
Our current code sets MIPS_CACHE_VTAG for the D-cache, but that flag
only has any effect for the I-cache. Additionally MIPS_CACHE_PINDEX is
set for the D-cache if CP0.Config7.AR is also set for an affected
processor, leading to confusing information in the bootstrap log (the
flag isn't used beyond that).
So delete the setting of MIPS_CACHE_VTAG and rely on MIPS_CACHE_ALIASES,
set in a common place, removing I-cache coherency issues seen in GDB
testing with software breakpoints, gdbserver and ptrace(2), on affected
systems.
While at it add a little piece of explanation of what CP0.Config6.SYND
is so that people do not have to chase documentation.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8507/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This add south-bridge (SB700/SB710/SB800 chipset) ACPI platform driver
for Loongson-3. This will be used by EC (Embedded Controller, used by
laptops) driver and STR (Suspend To RAM).
[ralf@linux-mips.org: Fix build error if !CONFIG_CPU_LOONGSON3. Build
doesn't like it if no obj-* variable is defined at all in a Makefile.
Obviously this has not been tested on other platforms.]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9619/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
