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16 Commits

Author SHA1 Message Date
John Crispin
97b921087f MIPS: Change my email address 
The old address is no longer valid. Use the my new one instead.

Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13201/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2016-05-13 14:02:18 +02:00
Philipp Zabel
24bc827beb MIPS: lantiq: Make reset_control_ops const 
The reset_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Cc: kernel@pengutronix.de
Patchwork: https://patchwork.linux-mips.org/patch/12619/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2016-05-13 14:01:43 +02:00
John Crispin
9eb8c69e0b MIPS: lantiq: Force the crossbar to big endian 
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11450/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-11-11 08:38:23 +01:00
John Crispin
26cfdbe30d MIPS: lantiq: Initialize the USB core on boot 
There is a DWC2 USB core in these SoCs. To make USB work we need to first
reset and power the state machine. These are SoC specific registers and
not part of the actual USB core.

Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11449/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-11-11 08:38:21 +01:00
Hauke Mehrtens
6e80785267 MIPS: Lantiq: Fix check for return value of request_mem_region() 
request_mem_region() returns a pointer and not an integer with an error
value. A check for "< 0" on a pointer will cause problems, replace it
with not null checks instead. This was found with sparse.

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11395/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-11-11 08:37:34 +01:00
Hauke Mehrtens
eefee024b0 MIPS: Lantiq: Add support for gphy firmware loading for ar10 and grx390 
Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11389/
Patchwork: https://patchwork.linux-mips.org/patch/11398/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-11-11 08:37:18 +01:00
John Crispin
50128fe816 MIPS: lantiq: reboot gphy on restart 
A reboot sometimes lead to a none working phy. An explicit reboot fixes the
problem.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8044/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2014-11-24 07:45:17 +01:00
John Crispin
c530781c93 MIPS: lantiq: add reset-controller api support 
Add a reset-controller binding for the reset registers found on the lantiq
SoC.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8043/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2014-11-24 07:45:17 +01:00
John Crispin
d0c550dc36 MIPS: lantiq: add GPHY clock gate bits 
Explicitly enable the clock gate of the internal GPHYs found on xrx200.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4816/
 2013-02-17 00:15:17 +01:00
John Crispin
af14a456c5 MIPS: lantiq: adds code for booting GPHY 
The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to
boot them up.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4522
 2012-11-11 18:47:35 +01:00
John Crispin
15753b6586 MIPS: lantiq: fix bootselect bits on XRX200 SoC 
The XRX200 SoC family has a different register layout for reading the boot
selection bits.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4519
 2012-11-11 18:47:20 +01:00
John Crispin
a0392222d9 OF: MIPS: lantiq: implement OF support 
Activate USE_OF, add a sample DTS file and convert the core soc code to OF.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3803/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2012-05-21 14:31:49 +01:00
John Crispin
6697c69330 MIPS: lantiq: cleanup reset code 
Add 2 new soc specifc handlers and remove superflous pr_notice calls.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3705/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2012-05-15 17:49:23 +02:00
Ralf Baechle
ab75dc02c1 MIPS: Fix up inconsistency in panic() string argument. 
Panic() invokes printk() to add a \n internally, so panic arguments should
not themselves end in \n.  Panic invocations in arch/mips and elsewhere
are inconsistently sometimes terminating in \n, sometimes not.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2011-12-07 22:01:45 +00:00
John Crispin
4af92e7a68 MIPS: lantiq: use export.h in favour of module.h 
The code located at arch/mips/lantiq/ included module.h to be able to use
the EXPORT_SYMBOL* macros. These can now be directly included using
export.h.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2011-11-14 13:59:24 +00:00
John Crispin
8ec6d93508 MIPS: Lantiq: add SoC specific code for XWAY family 
Add support for the Lantiq XWAY family of Mips24KEc SoCs.

* Danube (PSB50702)
* Twinpass (PSB4000)
* AR9 (PSB50802)
* Amazon SE (PSB5061)

The Amazon SE is a lightweight SoC and has no PCI as well as a different
clock. We split the code out into seperate files to handle this.

The GPIO pins on the SoCs are multi function and there are several bits
we can use to configure the pins. To be as compatible as possible to
GPIOLIB we add a function

int lq_gpio_request(unsigned int pin, unsigned int alt0,
        unsigned int alt1, unsigned int dir, const char *name);

which lets you configure the 2 "alternate function" bits. This way drivers like
PCI can make use of GPIOLIB without a cubersome wrapper.

The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was
taken from a 2.4.20 source tree and was never really changed by me since then.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2249/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2011-05-19 09:55:41 +01:00