Merge "Xilinx Zynq changes for v3.17" from Michal Simek:
arm: Xilinx Zynq dt patches for v3.17
- Document and use new cadence serial binding
* tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: DT: Migrate UART to Cadence binding
tty: cadence: Document DT binding
+ Linux 3.16-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "omap dts changes for v3.17 merge window, part1" from Tony Lindgren:
First set of .dts changes for omaps for v3.17 merge window:
- Enable irqchip crossbar interrupt mapping. These changes
are based on an immutable irqchip branch set up by Jason
Cooper to make it easier to merge the related .dts changes.
- Removal of omap2 related static clock data that now comes
from device tree.
- Enabling of PHY regulators for various omaps
- Enabling of PCIe for dra7
- Add support for am437x starterkit
- Enable audio for for omap5
- Enable display and am335x-evmsk
* tag 'omap-for-v3.17/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (43 commits)
ARM: DTS: omap5-uevm: Enable basic audio (McPDM <-> twl6040)
ARM: DTS: omap5-uevm: Add node for twl6040 audio codec
ARM: DTS: omap5-uevm: Enable palmas clk32kgaudio clock
ARM: dts: dra7: Add dt data for PCIe controller
ARM: dts: dra7: Add dt data for PCIe PHY
ARM: dts: dra7: Add dt data for PCIe PHY control module
ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock
ARM: dts: dra7-evm: Add regulator information to USB2 PHYs
ARM: omap2plus_defconfig: enable TPS65218 configs
ARM: dts: AM437x: Add TPS65218 device tree nodes
ARM: dts: AM437x: Fix i2c nodes indentation
ARM: dts: AM43x: Add TPS65218 device tree nodes
ARM: dts: Add devicetree for Gumstix Pepper board
ARM: dts: dra7: add crossbar device binding
ARM: dts: dra7: add routable-irqs property for gic node
ARM: OMAP24xx: clock: remove legacy clock data
...
Signed-off-by: Olof Johansson <olof@lixom.net>
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Instead, copy the used constants from the header file to the source file.
This allows the code to be migrated under drivers folder where we don't
have access to the OMAP specific header files.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some of the machine specific header includes are no longer used, so remove
these from the source file. This allows migration of the file under clock
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some of the machine specific header includes are no longer used, so remove
these from the source file. This allows migration of the file under clock
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Helps to get rid of some runtime cpu_is_x checks. This also allows eventual
migration of the code under clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Currently DPLL code uses runtime cpu_is_343x checks to see if the DPLL
has freqsel fields in its control register or not. Instead, add a new
flag to the clk_features.flags and use this during runtime. Allows
eventual move of the DPLL code under clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses
clk_features data provided during boot. This avoids the need to use
cpu_is_X type checks runtime, and allows us to eventually move the
clock code under the clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Currently, same functionality is copy pasted in two locations. Instead,
add a private API for this and get rid of some duplicated code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
These are SoC specific and get their init values based on the SoC type.
Previously the values were hard coded within the DPLL clock code, but
having them inside the clock features avoids runtime cpu_is_X type checks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This shall be used to replace the cpu type checks around the clock code.
Actual bit values will be introduced in patches later.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Instead, copy the used bitfield definitions to the source file. Done in
preparation to migrate the clock implementation under clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
These are unnecessary, as the clock code is only used on OMAP4+ platforms
through clock registrations. This also allows to eventually migrate the
clock type implementation under clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The legacy-style definition of the hwmod addr space is no longer
required as AM33xx/AM43xx are DT-boot only, and the minimal mailbox
DT nodes have been added, so clean up this data.
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The legacy-style definition of the hwmod addr space is no longer
required after the addition of the OMAP4 mailbox DT node, so
clean up this data.
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <bcousson@baylibre.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP2 devices are devicetree boot only, and the legacy mode
of mailbox device creation should no longer be used, so remove
the mailbox attribute data and the hwmod addr space used for
creating mailboxes in legacy mode.
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The legacy platform device for mailbox should not be created for
a DT boot, so adjust the platform device initialization logic
appropriately.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the hwmod data for the 13 instances of the system mailbox
IP in DRA7 SoC. The patch is needed for performing a soft-reset
while configuring the respective mailbox instance, otherwise is
a non-essential change for functionality. The modules are smart
idled on reset, and the IP module mode is hardware controlled.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On OMAP SOCs using PL310 controllers, power_ctrl register is not
accessible from non-secure software even on PL310 versions which
support it. The secure code takes care of setting it up correctly
and power transitions are proven on these devices.
For example, AM437x has L2C-310 version r3p3 and ROM code on that
device does not support writing to L2C-310 power control register.
The L2C driver, however, tries writing to this register for all
revisions >= r3p0.
This leads to a warning dump on boot which leads most users to believe
that L2 cache is non-functional.
Since the problem is understood, and cannot be addressed through
software, replace the warning with a pr_info() while maintaining the
WARN_ON() for other truly unexpected scenarios.
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC controller supports up to 8 memory devices connected to it.
Since there is one statically allocated "struct platform_device
gpmc_nand_device" it is not possible to configure the system to
use more than one NAND device connected to the GPMC. This
modification makes it possible to use up to 8 NAND devices
connected to the GPMC controller.
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Signed-off-by: Roger Quadros <rogerq@ti.com>
This clock type declaration is no longer used as all omap4+ SoC clock
data has been moved to DT, thus remove it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The mach-omap2 directory contains full register defines for OMAP4
control module but only around 27 of those are used. There are is
a total of 1795 register defines in four files with only 27 in use.
That is pretty low usefulness ratio...
I guess alot more was used when we had omap4 board files and
mach-omap2 contained more drivers but this has now changed.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
[tony@atomide.com: updated to apply]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This code is not working currently and it can be removed. There is a
conflict in sharing resources with the actual HDMI driver and with
the ASoC HDMI audio DAI driver.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently, child nodes of the gpmc node are iterated and probed
regardless of their 'status' property. This means adding 'status =
"disabled";' has no effect.
This patch changes the iteration to only probe nodes marked as
available.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The DSP platform device for TI DSP/Bridge is currently
created unconditionally whenever CONFIG_TIDSPBRIDGE is
enabled. This device should only be created on OMAP34xx/
OMAP36xx SoCs, and not for other OMAP3 derived SoCs or when
booting multi-arch images on other SoCs. So, add a check for
the SoC family both before creating the device and allocating
the carveout memory for the device.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
omap44xx_restart is defined as a static void inline when DRA7/AM437X is
defined alone, which implies that the restart function is no longer
functional even though it is built in. So, fix the definition of the
same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
A struct member variable is set to the same value more than once
This was found using a static code analysis program called cppcheck.
Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The divider value provided to the _dpll_test_fint can reach value of
256 with J type DPLLs (USB etc.), which causes an overflow with the u8
datatype. Fix this by changing the parameter to be an int instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: changed type of 'n' to unsigned int]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add the sysconfig class bits for the Super Speed USB
controllers
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Get rid of optional clock as that is now managed by the
AHCI platform driver.
Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The commit 7be914f {ARM: OMAP3: PRM/CM: Cleanup unused header} removed
some of the macros used by the TI DSP/Bridge driver. This fixes the
following build errors when trying to build DSP/Bridge driver (disabled
at present), otherwise results in the following build errors:
drivers/staging/tidspbridge/core/tiomap3430.c:531:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430.c:531:31: note: each undeclared identifier is reported only once for each function it appears in
make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430.o] Error 1
make[3]: *** Waiting for unfinished jobs....
drivers/staging/tidspbridge/core/tiomap_io.c: In function 'sm_interrupt_dsp':
drivers/staging/tidspbridge/core/tiomap_io.c:404:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap_io.c:404:31: note: each undeclared identifier is reported only once for each function it appears in
drivers/staging/tidspbridge/core/tiomap_io.c:414:12: error: 'OMAP3430_IVA2_DPLL_FREQSEL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap_io.c:415:12: error: 'OMAP3430_EN_IVA2_DPLL_SHIFT' undeclared (first use in this function)
make[3]: *** [drivers/staging/tidspbridge/core/tiomap_io.o] Error 1
drivers/staging/tidspbridge/core/tiomap3430_pwr.c: In function 'dsp_clk_wakeup_event_ctrl':
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: error: 'OMAP3430_GRPSEL_GPT5_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: note: each undeclared identifier is reported only once for each function it appears in
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:455:19: error: 'OMAP3430_GRPSEL_GPT6_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:468:19: error: 'OMAP3430_GRPSEL_GPT7_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:481:19: error: 'OMAP3430_GRPSEL_GPT8_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:494:19: error: 'OMAP3430_GRPSEL_MCBSP1_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:546:19: error: 'OMAP3430_GRPSEL_MCBSP5_MASK' undeclared (first use in this function)
make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430_pwr.o] Error 1
make[2]: *** [drivers/staging/tidspbridge] Error 2
Fixes: 7be914f (ARM: OMAP3: PRM/CM: Cleanup unused header)
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Pull ARM SoC fixes from Olof Johansson:
"This week's arm-soc fixes:
- A set of of OMAP patches that we had missed Tony's pull request of:
* Reset fix for am43xx
* Proper OPP table for omap5
* Fix for SoC detection of one of the DRA7 SoCs
* hwmod updates to get SATA and OCP to work on omap5 (drivers
merged in 3.16)
* ... plus a handful of smaller fixes
- sunxi needed to re-add machine specific restart code that was
removed in anticipation of a watchdog driver being merged for 3.16,
and it didn't make it in.
- Marvell fixes for PCIe on SMP and a big-endian fix.
- A trivial defconfig update to make my capri test board boot with
bcm_defconfig again.
... and a couple of MAINTAINERS updates, one to claim new Keystone
drivers that have been merged, and one to merge MXS and i.MX (both
Freescale platforms).
The largest diffs come from the hwmod code for omap5 and the re-add of
the restart code on sunxi. The hwmod stuff is quite late at this
point but it slipped through cracks repeatedly while coming up the
maintainer chain and only affects the one SoC so risk is low"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
MAINTAINERS: Add few more Keystone drivers
MAINTAINERS: merge MXS entry into IMX one
ARM: sunxi: Reintroduce the restart code for A10/A20 SoCs
ARM: mvebu: fix cpuidle implementation to work on big-endian systems
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
ARM: mvebu: move Armada 375 external abort logic as a quirk
ARM: bcm: Fix bcm and multi_v7 defconfigs
ARM: dts: dra7-evm: remove interrupt binding
ARM: OMAP2+: Fix parser-bug in platform muxing code
ARM: DTS: dra7/dra7xx-clocks: ATL related changes
ARM: OMAP2+: drop unused function
ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm
ARM: dts: omap5: Update CPU OPP table as per final production Manual
ARM: DRA722: add detection of SoC information
ARM: dts: Enable twl4030 off-idle configuration for selected omaps
ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
Add DSS hwmod data for AM43xx.
Signed-off-by: Sathya Prakash M R <sathyap@ti.com>
[tomi.valkeinen@ti.com: added missing dispc flags]
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Felipe Balbi <balbi@ti.com> # on linux-next 5f295cdf5c5d
[paul@pwsan.com: fixed build break on AM43xx-only config]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Merge OMAP fixes from Tony Lindgren:
Fixes for omaps for issues discovered during the merge window and
enabling of a few features that had to wait for the driver
dependencies to clear.
The fixes included are:
- Fix am43xx hard reset flags
- Fix SoC detection for DRA722
- Fix CPU OPP table for omap5
- Fix legacy mux parser bug if requested muxname is a prefix of
multiple mux entries
- Fix qspi interrupt binding that relies on the irq crossbar
that has not yet been enabled
- Add missing phy_sel for am43x-epos-evm
- Drop unused gic_init_irq() that is no longer needed
And the enabling of features that had driver dependencies are:
- Change dra7 to use Audio Tracking Logic clock instead of a fixed
clock now that the clock driver for it has been merged
- Enable off idle configuration for selected omaps as all the kernel
dependencies for device tree based booting are finally merged as
this is needed to get the automated PM tests working finally with
device tree based booting
- Add hwmod entry for ocp2scp3 for omap5 to get sata working as
all the driver dependencies are now in the kernel and this patch
fell through the cracks during the merge window
* tag 'omap-for-v3.16/fixes-against-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: dra7-evm: remove interrupt binding
ARM: OMAP2+: Fix parser-bug in platform muxing code
ARM: DTS: dra7/dra7xx-clocks: ATL related changes
ARM: OMAP2+: drop unused function
ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm
ARM: dts: omap5: Update CPU OPP table as per final production Manual
ARM: DRA722: add detection of SoC information
ARM: dts: Enable twl4030 off-idle configuration for selected omaps
ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
Control module related PM initializations are now moved within control
module driver. Done in preparation to isolate the code to its own driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
