Minnie provides an elan,ekth3500 touchscreen over the display,
so add the necessary node to enable it.
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Similar to pinky, brain is a development model and probably also
nearing extinction. But to keep pinky from being lonely I'll keep
the two brain boards around as well, especially as they as well
have easily accessible dut-connectors.
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
For the license change:
Acked-by: Brian Norris <briannorris@chromium.org>
The edp-24m clock has two possible sources: the 24MHz oscillator as well
as an external 27MHz input. The power-on-default is the 27MHz clock which
is not supplied on all Rockchip boards. While on all current boards and
also all Veyron Chromebooks the bootloader seems to adapt the muxing to
the internal source, this doesn't seem to be the case on headless veyron
devices like brain and mickey making the edp-24m clock an orphan.
On the hardware side the 27m input also is not connected at all.
With the upcoming deferral of orphan-clocks this results in the power-
domain code deferring, as it cannot request the needed clock and if the
synchronous reset is sucessfullat all in this case is also unknown.
So fix that by making sure, the edp-24m clock is muxed to the internal
24MHz oscillator at all times.
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
The Allwinner A80 SoC has an NMI controller. NMI is an external
interrupt pin exclusely used with PMICs and other system critical
peripherals (such as RTC) in Allwinner's reference designs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Ethernet controller found in the Armada 38x SoC's family support
TCP/IP checksumming with frame sizes larger than 1600 bytes, however
only on port 0.
This commit enables it by setting 'tx-csum-limit' to 9800B in
'ethernet@70000' node.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
So far, only the bus clock has been assigned, but in reality the
SAI IP has for clock inputs. The driver has been updated to
make use of the additional clock inputs by c3ecef21c3 ("ASoC:
fsl_sai: add sai master mode support"). Due to a bug in the
clock tree, the audio clock has been enabled none the less by
the specified bus clock (see "ARM: imx: clk-vf610: fix SAI
clock tree"), which made master mode even without the proper
clock assigned working.
This patch completes the clock definition for SAI2. On Vybrid,
only two MCLK out of the four options are available (the first
being the bus clock itself). See chapter 8.10.1.2.3 of the
Vybrid Reference manual ("SAI transmitter and receiver options
for MCLK selection"). Note: The audio clocks are only required
in master mode.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Uart1 rxd is wakeup capable on DRA72 EVM. Hence, mark rxd line as
wakeup capable. This is similar to commit 66b0436977 ("ARM: dts:
dra7-evm: Mark uart1 rxd as wakeup capable") for DRA74 EVM.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The U8500 HREF TVK board actually has a large set of sensors, with
their interrupt lines connected using open drain electronics.
Configure the two accelerometers and two magnetometers so we get
all sensors to actually probe on boot.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
According to a commit on the ChromeOS kernel, the temperature of the Speedy
surface is over skin temperature spec. So adjust the thermal settings
to mimic the ChromeOS tree to stay within these spec limits.
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
In some cases the machine radiating is very poor,sometime the temperature
is rising very quickly on heavy loading.So we need have more frequent
polling and better granularity.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A80 dtsi.
Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A80 SoC has a consumer IR receiver, which is the same as
older SoCs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The main (24MHz) clock on the A80 is configurable via the PRCM address
space. The low power/speed (32kHz) clock is from an external chip, the
AC100.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This adds the supported PRCM clocks and reset controls to the A80 dtsi.
The DAUDIO module clocks are not supported yet.
Also update clock and reset phandles for r_uart.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add device tree entry for the error location module.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pinmux configurations for RGMII1 based CPSW Ethernet pins and
MDIO pins:
- default configuration required for module in active state,
- sleep configuration required for module in inactive state.
Add mac node with single slave device. Add nodes for davinci_mdio and
cpsw_emac0.
Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pinmux configuration for NAND specific GPMC pins.
Add description for GPMC controller. Add child node for NAND flash
including CM-T335 specific partition table to GPMC node.
Enable error-location module (ELM).
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pinmux configuration for I2C0 and I2C1 pins.
Add description for I2C0 bus, set clock frequency to 400kHz.
Add child nodes for 24c02 EEPROM and em3027 RTC on I2C0 bus.
Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add basic support for CompuLab cm-t335 module based on AM335X SoC.
CM-T335 is a tiny computer-on-module (CoM) / system-on-module (SoM)
The module is built around the Texas Instruments Sitara AM3352/4
system-on-chip.
The CPU is supplemented with up-to 512MB DDR3 and up-to 1GB of on-board
NAND storage, WiFi connected to SPI, Bluetooth, Analog audio, Gigabit
Ethernet, CAN bus.
Current patch adds support:
UART0 and GPIO LED
Detailed description can be found at the module site:
http://www.compulab.co.il/products/computer-on-modules/cm-t335/
Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
[uri.mashiach@compulab.co.il: the default RAM amount reduced to
128MB to support also the minimal module configuration]
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The schematic expects VAUX1 to be 3.0V attached to the debug port.
The schematic expects VAUX4 to be 1.8V.
VAUX4 powers VDDS_CSI2 on processor.
Signed-off-by: Adam Ford <adam.ford@logicpd.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
When used with the Logic PD development kit, this makes the I2C buses match
the BSP released by Logic PD.
Signed-off-by: Adam Ford <adam.ford@logicpd.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Setup UART2 for communication at 3MBps with flow control.
Signed-off-by: Adam Ford <adam.ford@logicpd.com>
[tony@atomide.com: dropped the kim changes, that binding has been removed]
Signed-off-by: Tony Lindgren <tony@atomide.com>
The development kit schematic expects VAUX1 to be 3.0V. Most users use the development kit as a reference.
The development kit schematic expects VAUX4 to be 1.8V. VAUX4 powers VDDS_CSI2 on processor. If the voltage is too high it could damage the processor.
If it's too low, it won't work.
Signed-off-by: Tony Lindgren <tony@atomide.com>
When used with the Logic PD development kit, this makes the I2C buses match
the BSP released by Logic PD.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add dma channel information to the gpmc. Although not enabled by
default this will allow prefetch-dma to be used.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the missing SPI controller DMA handler in the dm816x DT
node, only properties for the two channels on four were present.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Adds ti,timer-pwm property to timers 4 to 7 to permit usage of their
PWM output fonctionnality via the dmtimer driver.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Using constants for pinctrl allows better readability and removes
redundancy with comments. AM33XX_IOPAD allows us to use part of the
pinctrl physical address as in the TRM instead of an offset.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use the pinmux IOPAD macros to define the register as an offset from
the padconf physical address instead of the offset from padconf base.
This makes the DTS easier to read since matches the addresses listed
in the Technical Reference Manual.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use the pinmux IOPAD macros to define the register as an offset from
the padconf physical address instead of the offset from padconf base.
This makes the DTS easier to read since matches the addresses listed
in the Technical Reference Manual.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use the pinmux IOPAD macros to define the register as an offset from
the padconf physical address instead of the offset from padconf base.
This makes the DTS easier to read since matches the addresses listed
in the Technical Reference Manual.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use the pinmux IOPAD macros to define the register as an offset from
the padconf physical address instead of the offset from padconf base.
This makes the DTS easier to read since matches the addresses listed
in the Technical Reference Manual.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
