clk: tegra: Changes for v4.2-rc1
This contains the EMC clock driver that's been exhaustively reviewed and
tested. It also includes a change to the clock core that allows a clock
provider to perform low-level reparenting of clocks. This is required by
the EMC clock driver because the reparenting needs to be done at a very
specific point in time during the EMC frequency switch.
We are about to add a new driver to support new features like using the
TDMA engine to offload the CPU.
Orion, Dove and Kirkwood platforms are already using the mv_cesa driver,
but Orion SoCs do not embed the TDMA engine, which means we will have to
differentiate them if we want to get TDMA support on Dove and Kirkwood.
In the other hand, the migration from the old driver to the new one is not
something all people are willing to do without first auditing the new
driver.
Hence we have to support the new compatible in the mv_cesa driver so that
new platforms with updated DTs can still attach their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The mv_cesa driver currently expects the SRAM memory region to be passed
as a platform device resource.
This approach implies two drawbacks:
- the DT representation is wrong
- the only one that can access the SRAM is the crypto engine
The last point is particularly annoying in some cases: for example on
armada 370, a small region of the crypto SRAM is used to implement the
cpuidle, which means you would not be able to enable both cpuidle and the
CESA driver.
To address that problem, we explicitly define the SRAM device in the DT
and then reference the sram node from the crypto engine node.
Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Merge the mvebu/drivers branch of the arm-soc tree which contains
just a single patch bfa1ce5f38 ("bus:
mvebu-mbus: add mv_mbus_dram_info_nooverlap()") that happens to be
a prerequisite of the new marvell/cesa crypto driver.
Earlycon calculates UART clock as "BASE_BAUD * 16". In case of ARC
"BASE_BAUD" is calculated dynamically in runtime, basically it is an
alias to arc_early_base_baud(), which in turn just does
"arc_base_baud/16".
8250 UART on AXS/SDP board uses 33.3MHz clock source which is set in
"arc_base_baud" with this change.
Additional compatibility string "snps,arc-sdp" is introduced as well
because there're different flavours of AXS boards but they all share the
same motherboard and so it's possible to re-use the same code for
motherbord even if CPU daughterboard changes.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
The AXS10x platforms consist of a mainboard with peripherals,
on which several daughter cards can be placed. The daughter cards
typically contain a CPU and memory.
Signed-off-by: Mischa Jonker <mjonker@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Add DT binding documentation for lpc1850-cgu driver.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Remove old Cygnus dummy clock binding document, as it's replaced by
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
drm/panel: Changes for v4.2-rc1
This contains fixes for the long-standing build issues that some of the
bridge drivers were exposing. Other than that it's mostly cleanup and a
couple of new simple panels that are supported.
* tag 'drm/panel/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/panel: simple: Add bus format for HannStar HSD100PXN1
drm/panel: simple: Add display timing for HannStar HSD100PXN1
drm/panel: ld9040: Remove useless padding
drm/panel: Constify OF match tables
drm/bridge: Remove stale ptn3460.h include
drm/bridge: ps8622: Include linux/gpio/consumer.h
drm/bridge: ptn3460: Include linux/gpio/consumer.h
drm/bridge: dw-hdmi: Return number of EDID modes
drm/panel: simple: Add support for LG LB070WV8 800x480 7" panel
drm/bridge: ptn3460: Pass flags to devm_gpiod_get()
drm/bridge: ps8622: Pass flags to devm_gpiod_get()
drm/bridge: ptn3460: Fix I2C ID table to match the reported modalias
drm/bridge: dw-hdmi: Staticize dw_hdmi_bridge_funcs
The rk3368 is the first ARM64 soc from Rockchip, but seems to share most
peripherals with the ARM32 soc, including the pinctrl functionality.
The only notable difference is - as with every Rockchip soc - that the
offsets in the General Register Files moved around and a split of the pmu
section of the rk3288 into pmu and pmugrf (pmu general register files)
sections. The pinctrl driver of course only needs the pmugrf registers
for controlling the pin settings.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the device tree bindings document for the TI Wakeup M3 remote
processor devices on AM33xx and AM43xx SoCs. These devices are used
to offload low-level power management functionality, and are handled
by the wkup_m3 remoteproc driver.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
- add new property "atmel,fifo-size"
- change "cs-gpios" to optional for SPI controller version >= 2.
Please be aware that the VERSION register can not be used to guess the
size of FIFOs. Indeed, for a given hardware version, the SPI controller
can be integrated on Atmel SoCs with different FIFO sizes. Also the
"atmel,fifo-size" property is optional as older SPI controllers don't
embed FIFO at all.
Besides, the FIFO size can not be read or guessed from other registers:
When designing the FIFO feature, no dedicated registers were added to
store this size. Unused spaces in the I/O register range are limited and
better reserved for future usages. Instead, the FIFO size of each
peripheral is documented in the programmer datasheet.
Finally, on a given SoC, there can be several instances of the SPI
controller with different FIFO sizes. This explain why we'd rather use a
dedicated DT property than use the "compatible" property.
For instance, sama5d2x SoCs come with some SPI controllers, the ones
inside Flexcoms, integrating 32 data FIFOs whereas other SPI controllers
use 16 data FIFOs. All these SPI controllers share the same IP version.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add PFC support for the R8A7794 SoC including pin groups for some
on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF...
Sergei: squashed together several patches, fixed the MLB_CLK typo,
added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin
group names, removed stray new line and fixed typos in the comments
in the pinmux_config_regs[] initializer, removed the platform device
ID, took into account limited number of signals in the GPIO1/5/6
controllers, added reasonable and removed unreasonable
copyrights, modified the bindings document, renamed, added changelog.
Changes in version 5:
- resolved rejects, refreshed the patch;
- added Laurent Pinchart's ACK.
Changes in version 4:
- reused the PORT_GP_26() macro to #define PORT_GP_28().
Changes in version 3:
- removed the platform device ID;
- added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the
CPU_ALL_PORT() macro.
Changes in version 2:
- rebased the patch.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Ortiz says:
====================
NFC 4.2 pull request
This is the NFC pull request for 4.2.
- NCI drivers can now define their own handlers for processing
proprietary NCI responses and notifications.
- NFC vendors can use a dedicated netlink API to send their own
proprietary commands, like e.g. all commands needed to implement
vendor specific manufacturing tools.
- A new generic NCI over UART driver against which any NCI chipset
running on top of a serial interface can register.
- The st21nfcb driver is renamed to st-nci as it can and will support
most of ST Microelectronics NCI chipsets.
- The st21nfcb driver can put its CLF in hibernate mode and save
significant amount of power.
- A few st21nfcb minor fixes.
- The NXP NCI driver now supports ACPI enumeration.
- The Marvell NCI driver now supports both USB and serial
physical interfaces.
- The Marvell NCI drivers also supports NCI frames being muxed
over HCI. This is a setting that can be defined by a DT property.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
DSPI driver has been updated and support more compatible strings.
This patch update the DT binding documentation.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Some ECs need a little time for waking up before they can accept
SPI data at a high speed. Add a "google,cros-ec-spi-pre-delay"
property to the DT binding to configure this.
If this property isn't set, then no delay will be added. However,
if set it will cause a delay equal to the value passed to it to
be inserted at the beginning of a transaction.
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This is binding information for the UniPhier on-chip UART driver
(drivers/tty/serial/8250/8250_uniphier.c).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add support for the Hannstar HSD100PXN1 to the DRM simple panel driver.
The HSD100PXN1 is an XGA (1024x768) panel with an 18-bit LVDS interface.
It supports pixel clocks in the range of 55-75 MHz.
This panel is offered for sale by Freescale as a companion part to its'
i.MX5x Quick Start board and i.MX6 SABRE platforms with under the name
MCIMX-LVDS1.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some regulators can limit their input current (typically annotated
as ilim). Add an op (set_input_current_limit) and a DT property +
constraint to support this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Some regulators support a "soft start" feature where the voltage
ramps up slowly when the regulator is enabled. Add an op
(set_soft_start) and a DT property + constraint to support this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Some regulators need to be configured to pull down a resistor
when the regulator is disabled. Add an op (set_pull_down) and a
DT property + constraint to support this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Some regulators have a fixed load that isn't captured by
consumers that the kernel knows about. Add a constraint to
support this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add mclk-fs ratio property per dai-link sub node. This will
allow to manage several codecs with different ratio.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The Hardware Spinlock device on atlas7 provides hardware assistance
for synchronization between the multiple processors in the system
(dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
This patch adds the DT bindings information for this hwspinlock
module.
Reviewed-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Wei Chen <wei.chen@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
Few more omap device tree changes for v4.2 merge window:
- Add dm9000 Ethernet support to omap3-devkit8000
- Add Toby-Churchill SL50 board support
- Add vendor prefix for Toby Churchill Ltd
* tag 'omap-for-v4.2/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x-sl50: Add Toby-Churchill SL50 board support.
of: Add vendor prefix for Toby Churchill Ltd.
ARM: dts: omap3-devkit8000: Add dm9000 support
