The Maxim MAX77686 PMIC is a multi-function device with regulators,
clocks and a RTC. The DT bindings for the clocks are in a separate
file but the bindings for the regulators are inside the mfd part.
To make it consistent with the clocks portion of the binding and
because is more natural to look for regulator bindings under the
bindings/regulator sub-directory, split the regulator portion of
the DT binding and add it as a separate file.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The MAX77802 is a chip that contains regulators, 2 32kHz clocks,
a RTC and an I2C interface to program the individual components.
The are already DT bindings for the regulators and clocks and
these reference to a bindings/mfd/max77802.txt file, that didn't
exist, for the details about the PMIC.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The ePAPR standard says that: "the name of a node should be somewhat
generic, reflecting the function of the device and not its precise
programming model."
So, change the max77686 binding document example to use a generic
node name instead of using the chip's name.
Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The regulator-compatible property from the regulator DT binding was
deprecated. But the max77686 DT binding doc still suggest to use it
instead of the regulator node name's which is the correct approach.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Add support for the I2C controller found on several NXP devices
including LPC2xxx, LPC178x/7x and LPC18xx/43xx. The controller
is implemented as a state machine and the driver act upon the
state changes when the bus is accessed.
The I2C controller supports master/slave operation, bus
arbitration, programmable clock rate, and speeds up to 1 Mbit/s.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Based on i2c-mux-gpio driver, similarly the register-based mux
switch from one bus to another by setting a single register.
The register can be on PCIe bus, local bus, or any memory-mapped
address. The endianness of such register can be specified in device
tree if used, or in platform data.
Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Start a new file which describes the generic bindings used for I2C with
device tree. So we have a central place to look for them, increase
visibility of them, and hopefully reduce the amount of custom properties
introduced.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Introduce driver for he Atmel SDMMC available on sama5d2. It is a sdhci
compliant controller.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The pfc in the R8A7790 (and probably others in the R-Car gen 2 family)
supports switching SDHI signals between 3.3V and 1.8V nominal voltage,
and the SD driver should do that when switching to and from UHS modes.
Add a flag for pins that have configurable I/O voltage and SoC
operations to get and set the nominal voltage. Implement the pinconf
power-source parameter using these operations.
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Ortiz says:
====================
NFC 4.3 pull request
This is the NFC pull request for 4.3.
With this one we have:
- A new driver for Samsung's S3FWRN5 NFC chipset. In order to
properly support this driver, a few NCI core routines needed
to be exported. Future drivers like Intel's Fields Peak will
benefit from this.
- SPI support as a physical transport for STM st21nfcb.
- An additional netlink API for sending replies back to userspace
from vendor commands.
- 2 small fixes for TI's trf7970a
- A few st-nci fixes.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Add the devicetree descriptor for the Analog Devices AXI-DMAC DMA
controller. This is a soft peripheral used in FPGAs and the bindings
describe how it is connected to the system (clock, interrupt, memory map)
as well as the configuration options that were used when the peripheral was
instantiated.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This change documents a new property for the snps,dw-apb-ssi device,
allowing an implementer to specify either four byte or two bytes
access to the SPI controller data register.
This supports a change that unbreaks this driver on picoXcell
platforms.
Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
ARM: tegra: Devicetree changes for v4.3-rc1
Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on
Venice2 and Jetson TK1. This also enables support for the PMU hardware
found on Tegra124, which among other things, can be used for performance
measurements.
* tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Add gpio-ranges property
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
ARM: tegra: Add Tegra124 PMU support
ARM: tegra: jetson-tk1: Add GK20A GPU DT node
ARM: tegra: venice2: Add GK20A GPU DT node
ARM: tegra: Add IOMMU node to GK20A
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Enable the DFLL on the Jetson TK1
ARM: tegra: Add the DFLL to Tegra124 device tree
pinctrl: tegra: Only set the gpio range if needed
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
clk: tegra: Add Tegra124 DFLL clocksource platform driver
clk: tegra: Add DFLL DVCO reset control for Tegra124
clk: tegra: Introduce ability for SoC-specific reset control callbacks
clk: tegra: Add functions for parsing CVB tables
clk: tegra: Add closed loop support for the DFLL
clk: tegra: Add library for the DFLL clock source (open-loop mode)
clk: tegra: Add binding for the Tegra124 DFLL clocksource
Signed-off-by: Olof Johansson <olof@lixom.net>
ARM: tegra: CPU frequency scaling for v4.3-rc1
This adds CPU frequency scaling support for Tegra124.
* tag 'tegra-for-4.3-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
cpufreq: Add cpufreq driver for Tegra124
cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq
cpufreq: tegra124: Add device tree bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
ARM: tegra: Cleanup patches for v4.3-rc1
Just a couple of trivial cleanups to make the HDA controller driver code
match the device tree binding.
* tag 'tegra-for-4.3-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ALSA: hda/tegra: Order clock and reset names consistently
ALSA: hda/tegra - Fix hda2codec_2x clock and reset names
Signed-off-by: Olof Johansson <olof@lixom.net>
Reset controller changes for v4.3
- moved the DT reset binding includes from
include/dt-bindings/reset-controller to include/dt-bindings/reset
- new driver for LPC18xx Reset Generation Unit (RGU)
- of_device_id array in the STi driver changed to const.
- extend SoCFPGA reset driver to support Arria10
- new ath79 reset controller driver for AR71XX/AR9XXX
- new driver for Xilinx Zynq reset controller
* tag 'reset-for-4.3' of git://git.pengutronix.de/git/pza/linux:
reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
MIPS: ath79: Add the reset controller to the AR9132 dtsi
reset: Add a driver for the reset controller on the AR71XX/AR9XXX
devicetree: Add bindings for the ATH79 reset controller
reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property
doc: dt: add documentation for lpc1850-rgu reset driver
reset: add driver for lpc18xx rgu
reset: sti: constify of_device_id array
ARM: STi: DT: Move reset controller constants into common location
MAINTAINERS: add include/dt-bindings/reset path to reset controller entry
Signed-off-by: Olof Johansson <olof@lixom.net>
Add driver for Samsung S3FWRN5 NFC controller.
S3FWRN5 is using NCI protocol and I2C communication interface.
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This patch implements LED driver for PowerNV platform using the existing
generic LED class framework.
PowerNV platform has below type of LEDs:
- System attention
Indicates there is a problem with the system that needs attention.
- Identify
Helps the user locate/identify a particular FRU or resource in the
system.
- Fault
Indicates there is a problem with the FRU or resource at the
location with which the indicator is associated.
We register classdev structures for all individual LEDs detected on the
system through LED specific device tree nodes. Device tree nodes specify
what all kind of LEDs present on the same location code. It registers
LED classdev structure for each of them.
All the system LEDs can be found in the same regular path /sys/class/leds/.
We don't use LED colors. We use LED node and led-types property to form
LED classdev. Our LEDs have names in this format.
<location_code>:<attention|identify|fault>
Any positive brightness value would turn on the LED and a zero value would
turn off the LED. The driver will return LED_FULL (255) for any turned on
LED and LED_OFF (0) for any turned off LED.
The platform level implementation of LED get and set state has been
achieved through OPAL calls. These calls are made available for the
driver by exporting from architecture specific codes.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Acked-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Tested-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Acked-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This patch adds support for the DMA engine present on Allwinner A10,
A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
and dedicated. The main difference is in the mode of operation;
while a single normal channel may be operating at any given time,
dedicated channels may operate simultaneously provided there is no
overlap of source or destination.
Hardware documentation can be found on A10 User Manual (section 12), A13
User Manual (section 14) and A20 User Manual (section 1.12)
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This patch add support for Two Dimensional Animation and Compositing
Engine (2D-ACE) on the Freescale SoCs.
2D-ACE is a Freescale display controller. 2D-ACE describes
the functionality of the module extremely well its name is a value
that cannot be used as a token in programming languages.
Instead the valid token "DCU" is used to tag the register names and
function names.
The Display Controller Unit (DCU) module is a system master that
fetches graphics stored in internal or external memory and displays
them on a TFT LCD panel. A wide range of panel sizes is supported
and the timing of the interface signals is highly configurable.
Graphics are read directly from memory and then blended in real-time,
which allows for dynamic content creation with minimal CPU
intervention.
The features:
(1) Full RGB888 output to TFT LCD panel.
(2) Blending of each pixel using up to 4 source layers
dependent
on size of panel.
(3) Each graphic layer can be placed with one pixel resolution
in either axis.
(4) Each graphic layer support RGB565 and RGB888 direct colors
without alpha channel and BGRA8888 BGRA4444 ARGB1555 direct
colors
with an alpha channel and YUV422 format.
(5) Each graphic layer support alpha blending with 8-bit
resolution.
This is a simplified version, only one primary plane, one
framebuffer, one crtc, one connector and one encoder for TFT
LCD panel.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
The only reason why we had dmacap,* properties is because back when
DMA_MEMSET was supported, only one out of the two channels per engine
could do a memset operation. But this is something that the driver
already knows anyway, and since then, the DMA_MEMSET support has been
removed.
The driver is already well aware of what each channel supports and the
one to one mapping between Linux specific implementation details (such
as dmacap,interrupt enabling DMA_INTERRUPT) and DT properties is a
good indication that these DT properties are wrong.
Therefore, this commit simply gets rid of these dmacap,* properties,
they are now ignored, and the driver is responsible for knowing the
capabilities of the hardware with regard to the dmaengine subsystem
expectations.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
With more than two switches in a hierarchy, it becomes necessary to
describe multi-hop routes between switches. The current binding does
not allow this, although the older platform_data did. Extend the link
property to be a list rather than a single phandle to a remote switch.
It is then possible to express that a port should be used to reach
more than one switch and the switch maybe more than one hop away.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix up bogus RTC compatible change for am4372 and add missing
DPLL for am4372 cpsw Ethernet driver. Also add ARM global and
local timers for am4372.
* tag 'omap-for-v4.3/dt-pt4-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
arm: boot: dts: am4372: add ARM timers and SCU nodes
ARM: dts: AM4372: Add the am4372-rtc compatible string
ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock
ARM: dts: AM437X: add dpll_clksel_mac_clk node
Signed-off-by: Olof Johansson <olof@lixom.net>
Renesas ARM Based SoC CPG/MSTP Clock Driver Updates for v4.3
* Add Clock Domain support to the Clock Pulse Generator
(CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain.
* tag 'renesas-clk-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: Add CPG/MSTP Clock Domain support
Signed-off-by: Olof Johansson <olof@lixom.net>
The i.MX device tree updates for 4.3:
- Add audio and eTSEC device support and update dspi node for LS1021A.
- Add initial i.MX6UL and imx6ul-14x14-evk board support, and enable
a bunch of device support for i.MX6UL, including RTC, power key, USB,
QSPI, and dual FEC.
- Enable HDMI and LVDS dual display support for a few imx6qdl boards.
- Support of imx6sl-warp board rev1.12, the version which will be
publicly available for the customers.
- A few i.MX7D device additions, watchdog, cortex-a7 coresight
components, RTC, power key, power off.
- Some Vybrid updates: add device support for I2C, QSPI, eSDHC etc.,
update ADC node, and define stdout-path property.
- A few random updates for i.MX27 and i.MX53 devices.
* tag 'imx-dt-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits)
ARM: dts: imx6ul: add snvs power key support
ARM: dts: imx6ul: add RTC support
ARM: dts: imx6ul: enable GPC as extended interrupt controller
ARM: dts: imx6sx: correct property name for wakeup source
ARM: dts: add property for maximum ADC clock frequencies
ARM: dts: imx7d: enable snvs rtc, onoffkey and power off
ARM: dts: imx6ul-14x14-evk: add fec1 and fec2 support
ARM: dts: imx: add fec1 and fec2 nodes for SOC i.MX6UL
ARM: dts: imx27: add support of internal rtc
ARM: dts: vf-colibri: define stdout-path property
ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR
ARM: dts: ls1021a: Add the eTSEC controller nodes
ARM: dts: imx6ul: add qspi support
ARM: dts: imx6ul: fix low case define in imx6ul-pinfunc.h
ARM: dts: imx6ul: add usb host and function support
ARM: dts: vfxxx: Add io-channel-cells property for ADC node
ARM: dts: ls1021a: Add dts nodes for audio on LS1021A
ARM: imx6qdl-sabreauto.dtsi: enable USB support
ARM: dts: imx: update snvs to use syscon access register
ARM: dts: imx: add imx6ul and imx6ul evk board support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The i.MX SoC changes for 4.3:
- Add i.MX6 Ultralite SoC support, which is the newest addition to
i.MX6 family. It integrates a single Cortex-A7 core and a power
management module that reduces the complexity of external power
supply and simplifies power sequencing.
- Change SNVS RTC driver to use syscon interface for register access,
and add SNVS power key driver support.
- Add a second clock for mxc rtc driver, and support device tree probe
for the driver.
- Add FEC MAC reference clock and phy fixup initialization for i.MX6UL
platform.
* tag 'imx-soc-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
rtc: snvs: select option REGMAP_MMIO
ARM: imx6ul: add fec MAC refrence clock and phy fixup init
ARM: imx6ul: add fec bits to GPR syscon definition
rtc: mxc: add support of device tree
dt-binding: document the binding for mxc rtc
rtc: mxc: use a second rtc clock
input: snvs_pwrkey: use "wakeup-source" as deivce tree property name
Document: devicetree: input: imx: i.mx snvs power device tree bindings
input: keyboard: imx: add snvs power key driver
Document: dt: fsl: snvs: change support syscon
rtc: snvs: use syscon to access register
ARM: imx: add low-level debug support for i.mx6ul
ARM: imx: add i.mx6ul msl support
Signed-off-by: Olof Johansson <olof@lixom.net>
Add device tree bindings documentation for the
lpc1850-dmamux DMA router.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This introduces device tree bindings for the PL08x DMA controllers
when used with fixed signal assignment per channel, i.e. if each
channel on the PL08x is assigned precisely one burst/single signal
set.
[je: remove channel sub-node parsing, use cell value to assign AHB]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
SCFG provides SoC specific configuration and status registers for
the chip. Add this for powerpc platform.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
LTC3886 is a is a dual PolyPhase DC/DC synchronous step-down switching
regulator controller. It is mostly command compatible to LTC3883,
but supports two phases instead of one.
Suggested-by: Michael Jones <mike@proclivis.com>
Tested-by: Michael Jones <mike@proclivis.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
LTC2980 and LTM2987 are command compatible to LTC2977. They consist of
two LTC2977 on a single die, and are instantiated as two separate chips,
each supporting eight channels.
Suggested-by: Michael Jones <mike@proclivis.com>
Tested-by: Michael Jones <mike@proclivis.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
LTC2975 is mostly compatible to LTC2974, but supports input current
and power measurement.
Tested-by: Michael Jones <mike@proclivis.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Chanwoo writes:
Update extcon for v4.3
This patchset include the function update of extcon drivers without critical
update and fix minor issue of extcon drivers.
Detailed description for patchset:
1. Update the extcon drivers:
- Update the logic of microphone detection for extcon-arizona driver
- Support GPIO based USB ID detection of extcon-palmas driver
2. Fix minor issues:
- Clean code and remove the opitonal print_state() function pointer from extcon
core driver
- Clear interrupt bit state before requesting irq on extcon-max778433 driver
- Fix signedness bugs of extcon core driver
Before 5b83b2234b the driver was hard coding the wakeup irq to
be active low. The generic pm wakeirq does not override the active
high/low parameter, hence it must be specified correctly in the
device tree.
Mind that SDIO IRQ is active low as defined in the SDIO specification
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Several cap11xx variants have LEDs that be can be controlled; let's plug
the driver into the LED subsystem.
Signed-off-by: Matt Ranostay <mranostay@gmail.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
drm/panel: Changes for v4.3-rc1
This introduces support for a couple of new panels and also contains
some work to restructure the directories to get more consistency, to
deal better with more panel and bridge drivers getting added.
* tag 'drm/panel/for-4.3-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/bridge: Put Kconfig entries in a separate menu
drm/panel: Add support for LG LG4573 480x800 4.3" panel
drm/panel: Add display timing for Okaya RS800480T-7X0GP
of: Add Okaya Electric America vendor prefix
drm/panel: simple: Add support for NEC NL4827HC19-05B 480x272 panel
drm/panel: simple: Add support for AUO B080UAN01
drm/panel: simple: Correct minimum hsync length of the HannStar HSD070PWW1 panel
drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel
drm/bridge: Add vendor prefixes
drm/panel: Add Samsung prefix to panel drivers
drm/exynos: Remove PTN3460 dependency
drm/tegra: Changes for v4.3-rc1
There are a bunch of non-critical fixes here that I've collected over
the past few months, but the biggest part is Tegra210 support, in the
DC, DSI and SOR/HDMI drivers.
Also this finally restores DPMS with atomic mode-setting, something
that has been broken since the conversion and which I had originally
expected to take far less longer to fix.
* tag 'drm/tegra/for-4.3-rc1' of git://anongit.freedesktop.org/tegra/linux: (41 commits)
drm/tegra: sor: Add HDMI support
drm/tegra: sor: Add Tegra210 eDP support
drm/tegra: dc: Implement atomic DPMS
drm/tegra: sor: Restore DPMS
drm/tegra: dsi: Restore DPMS
drm/tegra: hdmi: Restore DPMS
drm/tegra: rgb: Restore DPMS
drm/tegra: sor: Use DRM debugfs infrastructure for CRC
drm/tegra: sor: Write correct head state registers
drm/tegra: sor: Constify display mode
drm/tegra: sor: Reset the correct debugfs fields
drm/tegra: sor: Set minor after debugfs initialization
drm/tegra: sor: Provide error messages in probe
drm/tegra: sor: Rename registers for consistency
drm/tegra: dpaux: Disable interrupt when detached
drm/tegra: dpaux: Configure pads as I2C by default
drm/tegra: dpaux: Provide error message in probe
drm/tegra: dsi: Add Tegra210 support
drm/tegra: dsi: Add Tegra132 support
drm/tegra: dsi: Add Tegra124 support
...
1) includes all the drm/msm side of things for upstream kernel working
on dragonboard 410c (still some pending work on adv7533 bridge chip)
2) initial support for msm8x94 (snapdragon 810)
3) support for msm8x74v1 (in addition to existing v2 support)
4) support for dma planes on mdp5 (additional planes that cannot scale/csc)
5) more yuv format support for mdp5 (single plane vyuy/uyvy/yuyv/yvyu,
two plane nv16/nv61, and three plane yuv420/yvu420)
6) rotation support for mdp5
7) initial hdcp support
8) fixes, etc
* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (46 commits)
drm/msm/dsi: Introduce DSI configuration module
drm/msm/dsi: Make each PHY type compilation independent
drm/msm/dsi: Split PHY drivers to separate files
drm/msm/dsi: Return void from msm_dsi_phy_disable()
drm/msm/dsi: Specify bitmask to set source PLL
drm/msm/mdp: Clear pending interrupt status before enable interrupt
drm/msm/mdp5: Add rotation (hflip/vflip) support to MDP5 planes (v2)
drm/msm: add calls to prepare and unprepare panel
drm/msm/dsi: Modify dsi manager bridge ops to work with external bridges
drm/msm/dsi: Allow dsi to connect to an external bridge
drm/msm/dsi: Create a helper to check if there is a connected device
drm/msm/dsi: Refer to connected device as 'device' instead of 'panel'
drm/msm/dsi: Make TE gpio optional
drm/msm: mdp4 lvds: get panel node via of graph parsing
drm/msm: dsi host: Use device graph parsing to parse connected panel
drm/msm: dsi host: add missing of_node_put()
drm/msm: Enable clocks during enable/disable_vblank() callbacks
drm/msm/mdp5: Add support for msm8x74v1
drm/msm/mdp5: Add DMA pipe planes for MDP5
drm/msm/mdp: Add capabilities to MDP planes (v2)
...
Pull ARM SoC fixes from Olof Johansson:
"A smallish batch of fixes, a little more than expected this late, but
all fixes are contained to their platforms and seem reasonably low
risk:
- a somewhat large SMP fix for ux500 that still seemed warranted to
include here
- OMAP DT fixes for pbias regulator specification that broke due to
some DT reshuffling
- PCIe IRQ routing bugfix for i.MX
- networking fixes for keystone
- runtime PM for OMAP GPMC
- a couple of error path bug fixes for exynos"
* tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: keystone: Fix the mdio bindings by moving it to soc specific file
ARM: dts: keystone: fix the clock node for mdio
memory: omap-gpmc: Don't try to save uninitialized GPMC context
ARM: imx6: correct i.MX6 PCIe interrupt routing
ARM: ux500: add an SMP enablement type and move cpu nodes
ARM: dts: dra7: Fix broken pbias device creation
ARM: dts: OMAP5: Fix broken pbias device creation
ARM: dts: OMAP4: Fix broken pbias device creation
ARM: dts: omap243x: Fix broken pbias device creation
ARM: EXYNOS: fix double of_node_put() on error path
ARM: EXYNOS: Fix potentian kfree() of ro memory
The dsi host looks for the connected panel node by parsing for a child
named 'panel'. This hierarchy isn't very flexible. The connected
panel is forced to be a child to the dsi host, and hence, a mipi dsi
device. This isn't suitable for dsi devices that don't use mipi dsi
as their control bus.
Follow the of_graph approach of creating ports and endpoints to
represent the connections between the dsi host and the panel connected
to it. In our case, the dsi host will only have one output port, linked
to the panel's input port.
Update DT binding documentation with device graph usage info.
v3:
- Fix return value checks of of_graph_* calls.
- Don't make port a mandatory DT property
- Fix defer check when no panel node specified
- Rename parse_dt func to align with other dsi_host funcs
Reviewed-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
For all of these devices, msm89xy was the lead chip, so standardize the
compatible names to align with convention used by rest of the qcom/msm
drivers.
Signed-off-by: Rob Clark <robdclark@gmail.com>
