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17 Commits

Author SHA1 Message Date
Alexander Shishkin
59d08d00d4 intel_th: pci: Add Ice Lake PCH support 
This adds Intel(R) Trace Hub PCI ID for Ice Lake PCH.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2018-09-18 16:08:38 +02:00
Alexander Shishkin
50352fa730 intel_th: Add SPDX GPL-2.0 header to replace GPLv2 boilerplate 
This adds SPDX GPL-2.0 header to the Trace Hub driver and removes the
GPLv2 boilerplate text.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
 2018-03-28 18:47:19 +03:00
Alexander Shishkin
24600840c7 intel_th: pci: Add Lewisburg PCH support 
This adds Intel(R) Trace Hub PCI ID for Lewisburg PCH.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2017-09-22 10:28:00 +02:00
Alexander Shishkin
920ce7c33d intel_th: pci: Add Cedar Fork PCH support 
This adds Intel(R) Trace Hub PCI ID for Cedar Fork PCH.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2017-09-22 10:28:00 +02:00
Alexander Shishkin
a0e7df335a intel_th: Perform time resync on capture start 
On some devices (TH 2.x devices at the moment), the internal time counter
is initially not synchronized to the global crystal clock, so the time
stamps it produces will not be useful. In this case, the driver needs
to force the time counter resync.

This applies the workaround to relevant devices.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
 2017-08-25 18:48:00 +03:00
Alexander Shishkin
3321371b5d intel_th: pci: Use drvdata for quirks 
Allow attaching miscellaneous quirk information to devices as drvdata.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
 2017-08-25 18:47:59 +03:00
Alexander Shishkin
efb3669e14 intel_th: pci: Add Cannon Lake PCH-LP support 
This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-LP.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: <stable@vger.kernel.org>
 2017-08-25 18:47:59 +03:00
Alexander Shishkin
84331e1390 intel_th: pci: Add Cannon Lake PCH-H support 
This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-H.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: <stable@vger.kernel.org>
 2017-08-25 18:47:58 +03:00
Alexander Shishkin
e9b2b3e793 intel_th: pci: Enable bus mastering 
The driver forgets to enable bus mastering for the PCI device.
Fix this.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
 2017-08-25 17:58:35 +03:00
Alexander Shishkin
340837f985 intel_th: pci: Add Gemini Lake support 
This adds Intel(R) Trace Hub PCI ID for Gemini Lake SOC.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
 2017-03-15 14:55:18 +02:00
Alexander Shishkin
5118ccd347 intel_th: pci: Add Denverton SOC support 
This adds Intel(R) Trace Hub PCI ID for Denverton SOC.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
 2017-03-15 14:55:17 +02:00
Alexander Shishkin
7a1a47ce35 intel_th: pci: Add Kaby Lake PCH-H support 
This adds Intel(R) Trace Hub PCI ID for Kaby Lake PCH-H.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: <stable@vger.kernel.org>
 2016-07-14 13:16:56 +03:00
Alexander Shishkin
aaa3ca8228 intel_th: pci: Add Broxton-M SOC support 
This adds Intel(R) Trace Hub PCI ID for Broxton-M SOC.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Reviewed-by: Laurent Fert <laurent.fert@intel.com>
 2016-04-19 22:54:05 +03:00
Alexander Shishkin
d7b1787161 intel_th: Set root device's drvdata early 
Already during the subdevice initialization time, devices will need
to reference Intel TH controller descriptor structure.

This patch moves setting the drvdata from the pci glue to intel_th
core, before subdevices are populated.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2016-02-20 14:09:14 -08:00
Alexander Shishkin
3f040887a8 intel_th: pci: Add Broxton SOC support 
This adds Intel(R) Trace Hub PCI ID for Broxton SOC.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2016-02-07 22:43:17 -08:00
Alexander Shishkin
6396b912f1 intel_th: pci: Add Apollo Lake SOC support 
This adds Intel(R) Trace Hub PCI ID for Apollo Lake SOC.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2016-02-07 22:43:17 -08:00
Alexander Shishkin
2b0b16d329 intel_th: Add pci glue layer for Intel(R) Trace Hub 
This patch adds basic support for PCI-based Intel TH devices. It requests
2 bars (configuration registers for the subdevices and STH channel MMIO
region) and calls into Intel TH core code to create the bus with subdevices
etc.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2015-10-04 20:28:58 +01:00