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10922 Commits

Author SHA1 Message Date
Huang Rui
1316956284 drm/amdgpu: load smc ucode at first with psp while rlc auto load is supported 
This patch loades smc ucode at first with psp while rlc auto load is supported
on navi10.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
bb67469e29 drm/amdgpu: enable psp front door loading by default on navi10 
Required for production hw and vddgfx.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
119eb6db54 drm/amdgpu/psp: skip mec jt when autoload is enabled 
When autoload is enabled, there is no need to load mec jt,
RLC will handle it automatically

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
cc0beec2dd drm/amd/amdgpu: add flag to mark whether autoload is supported or not 
rlc autoload is supported since navi10

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
1d1f41cf49 drm/amdgpu/psp: initialize autoload_supported flag in psp_sw_init 
RLC autoload is supported since from Navi10

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
4414ec6d14 drm/amdgpu/psp: update psp gfx interface to match with psp fw (v2) 
new psp gfx cmd is introuduced for rlc autoload

v2: rebase (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
fba08a77bb drm/amdgpu/psp: perform tmr_init and asd_init after loading sysdrv/sos 
Since from navi10, the tmr_size should be decided by psp sos according to
toc header. Driver should issue LOAD_TOC to psp sos to get the tmr_size needed.
The allocation of tmr_size then should be done only when sos/sysdrv loading
completed

Accordingly, asd_init also move to psp_hw_start after sos fw loading to make
calling sequence consistent.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
5160709d45 drm/amdgpu/psp: switch to use sos_offset_bytes member as sys_bin_size 
Navi10 will have toc built-in sos binary so that using header.ucode_size_bytes
minus sos_size_bytes actually is not sys_bin_size.

Using sos_offset_bytes works for both vega20 (psp_firmware_header_v1_0) and
navi10 (psp_firmware_header_v1_1)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
1a5b4cca29 drm/amdgpu/psp: start rlc autoload after psp recieved all gfx firmware 
RLC handles firmware loading for gfx to support vddgfx feature.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:50 -05:00
Hawking Zhang
7ea49e7651 drm/amdgpu/psp: add support to load TOC to psp 
Add support for the new load TOC command.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Hawking Zhang
46ea9501fb drm/amdgpu/psp: add structure to support load toc in psp (v2) 
Update the psp interface for the new commands.

v2: rebase (Alex)

FIXME:
GFX_CMD_ID_PROG_REG     = 0x0000000B,   /* program regs */
GFX_CMD_ID_LOAD_TOC     = 0x0000000B,   /* Load TOC and obtain TMR size */

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Hawking Zhang
434dbb2a4a drm/amdgpu/psp: support print out psp firmware header v1_1 info 
Support version 1.1.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Hawking Zhang
37e919180c drm/amdgpu/psp: print out psp v11 ucode hdr in drm debug mode 
Print the psp header data if requested.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Hawking Zhang
6fa405646d drm/amdgpu: add helper function to print psp hdr 
print the psp header data like we do for other firmwares.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Hawking Zhang
4a94ba8f37 drm/amdgpu: rename rlc autoload to backdoor autoload 
This is to differentiate rlc backdoor autoload from rlc
frontdoor autoload

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Hawking Zhang
52718c844c drm/amdgpu: use rlc toc from psp sos binary 
Instead of putting toc into driver source code, the toc will
be part of psp_sos fw. Driver need to get and parse it from
psp fw

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Hawking Zhang
93d8f2221b drm/amdgpu/psp: support init psp sos microcode with build-in toc 
psp_firmware_header_v1_1 is used for psp sos with build-in toc

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Hawking Zhang
7d0906e83a drm/amdgpu: add structure to support build-in toc to psp sos 
Table Of Content (TOC) is used by RLC to auto load gc firmwares.
PSP need to parse the toc to calculate the tmr size needed and
load gc firmwares to tmr for RLC to auto load them finally

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Tao Zhou
bc290fe552 drm/amdgpu: Add psp 11.0 support for navi10. 
Add psp 11.0 code for navi10. psp 11.0 is not enabled for now.
Will enable it when psp 11.0 firmware is available.

Signed-off-by: Tao Zhou <Tao.Zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:46:49 -05:00
Huang Rui
9dd4b75cf0 drm/amdgpu: set navi10's fw loading type as direct 
For bring up.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:36:15 -05:00
Le.Ma
5cc036a847 drm/amdgpu: add fw load type flag for rlc autoload 
Add another firmware load type AMDGPU_FW_LOAD_RLC_AUTO to support firmware
autoloading new feature in gfx10.

This flag can be leveraged for future engines that need autoload fw.

Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:36:11 -05:00
Le.Ma
2beae55e39 drm/amdgpu: add structures for buffer allocate/release for rlc autoload 
Allocate a visible framebuffer to store all gfxip ucodes as the format of TOC.

Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:36:07 -05:00
Hawking Zhang
edc611475a drm/amdgpu: add navi10 ih ip block (v3) 
IH is the interrupt handler block.

v1: add initial ih support (Ray)
v2: add dummy prescreen iv function for navi10 (Hawking)
v3: squash in additional updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:30 -05:00
Hawking Zhang
5527cd0640 drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/ 
interrupt source packet definitions for the display block (DCN).

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:30 -05:00
Hawking Zhang
abade675e0 drm/amdgpu: add irq sources for vcn v2_0 (v2) 
Add the interrupt source packet definitions.

v2: update (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:30 -05:00
Hawking Zhang
4984dd069f drm/amdgpu: add irq sources for sdma v5_0 
Add the interrupt source packet definitions.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
cb3908c133 drm/amdgpu: add irq sources for gfx v10_1 
Add the interrupt source packet definitions.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
f9df67e924 drm/amdgpu: add gmc v10 ip block for navi10 (v6) 
GMC in the GPU memory controller.

v1: add place holder and initial basic implementation (Ray)
v2: retire unused amdgpu_gart_set_defaults (Hawking)
v3: re-work get_vm_pde function (Hawking)
v4: replace legacy amdgpu_vram/gtt_location with
    amdgpu_gmc_vram/gtt_location (Hawking)
v5: squash in updates (Alex)
v6: use get_vbios_fb_size (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
adc43c1b5e drm/amdgpu: add mmhub v2 block for navi10 (v4) 
mmhub is the memory controller hub for multi-media (VCN).

v1: add place holder and initial functions (Ray)
v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
770b93e9ee drm/amdgpu: add gfxhub v2.0 block for navi10 (v4) 
gfxhub is the memory controller hub for gfx and sdma.

v1: add place holder and initial basic functions (Ray)
v2: replace the refernce to legacy mc structure with gmc structure
    remove the direct use of gart.table_addr (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Jack Xiao
7f95167ce1 drm/amdgpu: refine the PTE encoding of PRT for navi10 
Due to GCR change from navi10, the PTE encoding of PRT
needs change VSCTL = 01111 (was 0XX1X).

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
7596ab68ff drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10 
To differentiate the mtypes across asics.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
c304b9e519 drm/amdgpu: correct pte mtype field for navi 
The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Jack Xiao
367adb2ad5 drm/amdgpu/athub2: enable athub2 clock gating 
Enable athub2 clock gating and light sleep

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
9faa494e2f drm/amdgpu: add flag to support IH clock gating 
Add new flag for IH (interrupt handler) clockgating.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:25:52 -05:00
Hawking Zhang
714ff85251 drm/amdgpu: add new HDP CG flags 
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/
DS (Deep Sleep)/SD (Shut Down) modes are supported. However,
only one of these modes can be enabled at one time.

There is no dynamic power mode switch support. clock/power gating
has to be disabled before making any power mode change.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:25:46 -05:00
Hawking Zhang
54fc447279 drm/amdgpu: create mqd for gfx queues on navi10 
mqd is the memory queue descriptor for gfx and compute.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Jack Xiao
5bfca06928 drm/amdgpu: enable async gfx ring by default 
VDDGFX requires gfx queue to be installed via MAP_QUEUES packet.
Hence, enable async gfx ring by default.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Hawking Zhang
51bcce4621 drm/amdgpu: add module parameter for async_gfx_ring enablement 
0 means disable async_gfx_ring and is the default setting
1 means enable async_gfx_ring

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Hawking Zhang
53b2fe415f drm/amdgpu: enable gfx eop interrupt per gfx pipe 
Navi10 has 2 gfx pipe and need to enable gfx eop interrupt
per pipe, instead of enable eop int for all gfx pipes at one
time.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Jack Xiao
1919196165 drm/amdgpu/gfx10: add special unmap_queues packet for preemption 
CP introduced a special unmap_queues packet for gfx preemtion.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Hawking Zhang
849aca9f9c drm/amdgpu: Move common code to amdgpu_gfx.c 
move common code to amdgpu_gfx_enable_kcq,so
this function can be shared with gfx8 and gfx9

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:24:54 -05:00
Rex Zhu
ba0c13b774 drm/amdgpu: Add common gfx func Disable kcq via kiq 
so can be shared with gfx8 and gfx9

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:21:06 -05:00
Rex Zhu
bc4a6f7135 drm/amdgpu: Add struct kiq_pm4_funcs into kiq struct 
kiq can support 4 pm4 scheduler packets
set_resource, map_queues, unmap_queues, query_status.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:57 -05:00
Hawking Zhang
4fc6a88f01 drm/amdgpu: rename amdgpu_gfx_compute_mqd_sw_init 
The function now will create mqd bos for both gfx queue and compute queue

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:51 -05:00
Hawking Zhang
7470bfcf20 drm/amdgpu: add helper function for gfx queue/bitmap transition 
Similar to what we do for compute already.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:27 -05:00
Hawking Zhang
e537c99461 drm/amdgpu: acquire available gfx queues 
currently, amdgpu will owns the first gfx queue of each pipe
they are:
me:0 pipe:0 queue:0
me:0 pipe:1 queue:0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:17 -05:00
Hawking Zhang
cf02b03f7c drm/amdgpu: add members in amdgpu_me for gfx queue 
Update the structure for gfx10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:20:02 -05:00
Hawking Zhang
8825af65ff drm/amdgpu/gfx10: new approach to load gfx10 me fw (v4) 
gfx10 allows to only upload me jumptable while save the whole
me image at gtt memory.

v2: program CP_ME_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create me fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:19:56 -05:00
Hawking Zhang
2a00bb1322 drm/amdgpu/gfx10: new approach to load ce fw (v4) 
gfx10 allows to only upload ce jumptable while save the whole
ce image at gtt memory.

v2: program CP_CE_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create ce fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:19:52 -05:00