There is no need to have channel offset defined since all BayTrail and Braswell
ports are 1 channel. Remove unneeded definition.
While here, remove comment which has no value.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The managed API provides a better approach to help with acquiring and releasing
resources. Besides that error handling becomes simpler.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
WCH382 2S board is a PCIe card with 2 DB9 COM ports detected as
Serial controller: Device 1c00:3253 (rev 10) (prog-if 05 [16850])
Signed-off-by: Jeremy McNicoll <jmcnicol@redhat.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Considering that pci_pericom_setup(()'s only difference to
pci_default_setup() is the setting of the uartclk field, and taking
into account that this field already gets taken care of by having the
base_baud field filled in the pci_boards[] entries, there's no need
for both the function and the quirks table entry.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Intel MID UART quirks require already quite a bit of code
in 8250_pci.c. On new Intel platforms where it is used, the
integrated DMA engine no longer has its own PCI device, but
is instead configured from the UART's MMIO. That means we
will have to add even more code for handling just MID UARTs.
Instead of adding that to 8250_pci.c, splitting the support
of Intel MID UART into its own driver. Handling of the
integrated DMA engine becomes much simpler this way. Own
driver will also remove the need for things like specific
set_termios hooks for every board using this UART, and
simplify the handling of it in general.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Fix RS232/485 mode incorrect setting after S3/S4 resume for F81504/508/512
We had add RS232/485 RTS control with fecf27a373. But when it
resume from S3/S4, the mode register 0x40 + 0x08 * idx + 7 will
rewrite to 0x01 (RS232 mode).
This patch will modify 2 sections.
One is pci_fintek_init(), if it called when first init, it will
write mode register with 0x01. If it called from S3/S4 resume,
it's will get the relative port data and pass it to
pci_fintek_rs485_config() with NULL rs485 parameter.
The another modification is in pci_fintek_rs485_config(). It'll
re-apply old configuration when the parameter rs485 is NULL.
Signed-off-by: Peter Hung <hpeter+linux_kernel@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
According to DesignWare 8250 spec, if auto flow control
mode is enabled, a change in CTS does not cause an interrupt,
so sw-assisted CTS flow control mode will not work properly.
There reported an GPS firmware download failure issue, and we
verified the root cause is, the default sw-assisted CTS flow
control mode can not work properly since no interrupt when got
CTS signal.
This patch is to enable auto CTS mode by defaut if CRTSCTS
is enable for DesignWare 8250 controller.
Signed-off-by: Huiquan Zhong <huiquan.zhong@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
Reviewed-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add RS485 control for Fintek F81504/508/512
F81504/508/512 can control their RTS with H/W mode.
PCI configuration space for each port is 0x40 + idx * 8 + 7.
When it set with 0x01, it's configured with RS232 mode.
RTS is controlled by MCR.
When it set with 0x11, it's configured with RS485 mode.
RTS is controlled by H/W, RTS low with idle & RX, high with TX.
When it set with 0x31, it's configured with RS485 mode.
RTS is controlled by H/W, RTS high with idle & RX, low with TX.
We will force 0x01 on pci_fintek_setup().
Signed-off-by: Peter Hung <hpeter+linux_kernel@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The internal clock of the master chip, which is usually 125MHz, is only half
(62.5MHz) for the slave chips. So we have to adjust the uartclk for all the
slave ports. Therefor we add a new function to determine if a slave chip is
present and update pci_xr17v35x_setup accordingly.
Signed-off-by: Soeren Grunewald <soeren.grunewald@desy.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The Exar XR17V358 can also be combined with a XR17V354 chip to act as a
single 12 port chip. This works the same way as the combining two XR17V358
chips. But the reported device id then is 0x4358.
Signed-off-by: Soeren Grunewald <soeren.grunewald@desy.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The Exar XR17V358 chip usually provides only 8 ports. But two chips can be
combined to act as a single 16 port chip. Therefor one chip is configured
as master the second as slave by connecting the mode pin to VCC (master)
or GND (slave).
Then the master chip is reporting a different device-id depending on
whether a slave is detected or not. The UARTs 8-15 are addressed from
0x2000-0x3fff. So the offset of 0x400 from UART to UART can be used to
address all 16 ports as before.
See: https://www.exar.com/common/content/document.ashx?id=1587 page 11
Signed-off-by: Soeren Grunewald <soeren.grunewald@desy.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Serial ports of F81504/F81508/F81512 will failed when wakeup from S3(STR).
It's due to when the system wakeup from S3(STR), this PCI device's
configuration space from 0x40 to 0x40 + max_port * 0x08 should be
re-configured.
We move all initialization from pci_fintek_setup() to pci_fintek_init() and
set it to pci_serial_quirks .init section. It's will re-init this device when
system wakeup from pciserial_resume_ports().
Signed-off-by: Peter Hung <hpeter+linux_kernel@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Intel Tangier contains 4 HSUART ports as found on Intel Edison board which are
8250 compatible. The patch adds necessary bits to the driver.
Note that the HSU port0 is currently unavailable and thus not supported.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch replaces a switch-case by a formula using rational best
approximation that does necessary calculations for intel_mid_set_termios().
Below is a list of the calculations done for all defined baud rates. Each line
in a format: 1) nominator, 2) denominator, 3) prescaler, 4) Fuart, 5) port UART
clock, 6) list of baud rates with DLAB values.
24 25 12 48000000 64000000 4000000(1)
49 50 14 49000000 56000000 3500000(1)
4 5 16 40000000 40000000 2500000(1)
16 25 16 32000000 32000000 500000(4),1000000(2),2000000(1)
24 25 16 48000000 48000000 1500000(2),3000000(1)
2304 3125 16 36864000 36864000 576000(4),1152000(2)
8192 15625 16 26214400 26214400 50(32768),200(8192)
9216 15625 16 29491200 29491200 1800(1024),57600(32),115200(16),
230400(8),460800(4),921600(2),1843200(1)
12288 15625 16 39321600 39321600 75(32768),150(16384),300(8192),
600(4096),1200(2048),2400(1024),4800(512),
9600(256),19200(128),38400(64)
45056 78125 16 28835840 28835840 110(16384)
274432 390625 16 3512729635127296 134(16384)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Peter Hurley <peter@hurleysoftware.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch replaces a switch-case by a formula using rational best
approximation that does necessary calculations for byt_set_termios().
Below is a list of the calculations done for all defined baud rates. Each line
in a format: 1) numerator, 2) denominator, 3) prescaler, 4) Fuart, 5) port UART
clock, 6) list of baud rates with DLAB values.
4 5 16 80000000 80000000 2500000(2)
14 25 16 56000000 56000000 3500000(1)
16 25 16 64000000 64000000 500000(8),1000000(4),2000000(2),
4000000(1)
24 25 16 96000000 96000000 1500000(4),3000000(2)
2180 3103 16 70254592 70254592 134(32768)
2304 3125 16 73728000 73728000 576000(8),1152000(4)
8192 15625 16 52428800 52428800 50(65536),200(16384)
9216 15625 16 58982400 58982400 1800(2048),57600(64),115200(32),
230400(16),460800(8),921600(4),1843200(2)
12288 15625 16 78643200 78643200 75(65536),150(32768),300(16384),
600(8192),1200(4096),2400(2048),
4800(1024),9600(512),19200(256),38400(128)
9893 17154 16 57671680 57671680 110(32768)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Peter Hurley <peter@hurleysoftware.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Intel Penwell supports 3 HSUART ports which are 8250 compatible. The patch adds
necessary bits to the driver.
The functions have intel_mid_* prefix due to more than one platform will use
this code.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Convert the legacy system PM callbacks to new ones. Meanwhile, remove the
redudant calls to the PCI for changing a power state since it's done by bus
code.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
These quirk entries have the same effect as default
quirk entry, so we can just delete them.
Signed-off-by: Wang YanQing <udknight@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Commit 8b5c913f7e
("serial: 8250_pci: Add WCH CH352 quirk to avoid Xscale detection")
trigger one redundant entry report message.
This patch fix it.
Reported-by: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Wang YanQing <udknight@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
WCH384 4S board is a PCI-E card with 4 DB9 COM ports detected as
Serial controller: Device 1c00:3470 (rev 10) (prog-if 05 [16850])
Signed-off-by: Sergej Pupykin <ml@sergej.pp.ru>
Acked-by: Zany Yan <sirlight@cox.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The original driver fixed the io address with 0xe000+idx*8,
but real io address assigned from BIOS is dynamically from
read PCI configure space 0x24, 0x20, 0x1c.
The Fintek F81504/F81508/F81512 maybe malfunction without
this patch and malfunction surely when more then 1 PCI card.
Signed-off-by: Peter Hung <hpeter+linux_kernel@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
WCH382 is a PCI-E card with 1 LPT and 2 DB9 COM ports detected as
Serial controller: Device 1c00:3250 (rev 10) (prog-if 05 [16850])
Signed-off-by: Sergej Pupykin <ml@sergej.pp.ru>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Check the return value of ioremap_nocache to make sure we got a
valid mapping.
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Added recognition of EndRun Technologies PCIe PTP slave card
and setup two ttySx ports for communication with the card for
retrieval of PTP based time and to communicate with the card's
Linux OS.
Signed-off-by: Mike Skoog <mskoog@endruntechnologies.com>
Signed-off-by: Mike Korreng <mkorreng@endruntechnologies.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Pull slave-dmaengine updates from Vinod Koul:
"For dmaengine contributions we have:
- designware cleanup by Andy
- my series moving device_control users to dmanegine_xxx APIs for
later removal of device_control API
- minor fixes spread over drivers mainly mv_xor, pl330, mmp, imx-sdma
etc"
* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (60 commits)
serial: atmel: add missing dmaengine header
dmaengine: remove FSLDMA_EXTERNAL_START
dmaengine: freescale: remove FSLDMA_EXTERNAL_START control method
carma-fpga: move to fsl_dma_external_start()
carma-fpga: use dmaengine_xxx() API
dmaengine: freescale: add and export fsl_dma_external_start()
dmaengine: add dmaengine_prep_dma_sg() helper
video: mx3fb: use dmaengine_terminate_all() API
serial: sh-sci: use dmaengine_terminate_all() API
net: ks8842: use dmaengine_terminate_all() API
mtd: sh_flctl: use dmaengine_terminate_all() API
mtd: fsmc_nand: use dmaengine_terminate_all() API
V4L2: mx3_camer: use dmaengine_pause() API
dmaengine: coh901318: use dmaengine_terminate_all() API
pata_arasan_cf: use dmaengine_terminate_all() API
dmaengine: edma: check for echan->edesc => NULL in edma_dma_pause()
dmaengine: dw: export probe()/remove() and Co to users
dmaengine: dw: enable and disable controller when needed
dmaengine: dw: always export dw_dma_{en,dis}able
dmaengine: dw: introduce dw_dma_on() helper
...
It should not be used together with Auto Flow Control, and
Auto Flow Control is always enabled on Baytrail.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Quark X1000 contains two designware derived 8250 serial ports.
Each port has a unique PCI configuration space consisting of
BAR0:UART BAR1:DMA respectively.
Unlike the standard 8250 the register width is 32 bits for RHR,IER etc
The Quark UART has a fundamental clock @ 44.2368 MHz allowing for a
bitrate of up to about 2.76 megabits per second.
This patch enables standard 8250 mode
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
That field has been deprecated in favour of getting the necessary information
from ACPI or DT.
However, we still need to deal systems that are PCI only (no ACPI to back up)
like Intel Bay Trail. In order to support such systems, we explicitly bind
setup() to the appropriate DMA filter function and its corresponding parameter.
Then when serial8250_request_dma() doesn't find the channel via ACPI or DT, it
falls back to use the given filter function.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This Multi-IO card has one serial 16550-like and one parallel port connector.
Here's the lspci output, after this commit is applied:
03:07.0 Serial controller: Device 4348:5053 (rev 10) (prog-if 02 [16550])
Subsystem: Device 4348:5053
Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 21
Region 0: I/O ports at cf00 [size=8]
Region 1: I/O ports at ce00 [size=8]
Kernel driver in use: parport_serial
Kernel modules: 8250_pci, parport_serial
This commit adds an entry with the device ID to the blacklist declared in
8250_pci to prevent the driver from taking ownership. Also, and as was done
for the 2S/1P variant, add a quirk to skip autodetection and set the correct
type to 16550A clone.
Proper entries are added to parport_serial, to support the device parallel
and serial ports.
Cc: Gianluca Anzolin <gianluca@sottospazio.it>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
