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7499 Commits

Author SHA1 Message Date
Boyuan Zhang
914b5f53d0 drm/amdgpu: rename macro for VCN1.0 
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0
These two macros are used specifically for VCN1.0, therefore rename
it from general name to VCN1.0 specific name.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Boyuan Zhang
14539809bd drm/amdgpu: add internal reg offset translation for VCN inst 1 
Add range for vcn instance 1 for translation for internal register offset, which
is needed for VCN3.0

V2: update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Boyuan Zhang
c0f136ee8d drm/amdgpu: set indirect sram mode for VCN3.0 
Use indirect sram for secure DPG mode

V2: update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Boyuan Zhang
cfcc06cd15 drm/amdgpu: add pause DPG mode for VCN3.0 
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0

V2: update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Boyuan Zhang
65b17cc898 drm/amdgpu: add stop DPG mode for VCN3.0 
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0

V2: update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Boyuan Zhang
ec2d0577b4 drm/amdgpu: add start DPG mode for VCN3.0 
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0

V2: Separate from previous patch-0002, and update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Boyuan Zhang
99541f392b drm/amdgpu: add mc resume DPG mode for VCN3.0 
Add vcn_v3_0_mc_resume_dpg_mode to resume memory controller in DPG mode for VCN3.0

V2: Separate from previous patch-0002, and update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Boyuan Zhang
063cabd8b6 drm/amdgpu: add clock gating DPG mode for VCN3.0 
Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for VCN3.0

V2: Separate from previous patch-0002, and update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Likun Gao
046c18f4b8 drm/amdgpu: update golden setting for sienna_cichlid 
Update golden setting for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:12 -04:00
Kenneth Feng
846938c223 drm/amd/powerplay: enable mmhub pg 
mmhub pg can be obvserved from PCTL_CTRL

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Kenneth Feng
b794616d1f drm/amd/powerplay: enable athub pg 
enable athub pg and the status can be checked in
ATHUB_MISC_CNTL.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Le Ma
b770f04ba2 drm/amdgpu: skip VM inv eng assignment for mes ring 
Statically allocated VM inv eng of gfxhub on sienna_cichlid is used up.
Also VM inv eng is no need for mes ring.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Le Ma
7cf609b915 drm/amdgpu/mes: allocate memory slots for hw resource setting 
Pass a piece of memory to MES ucode to fill contents.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Le Ma
ae4e3b62df drm/amdgpu/mes: add status fence memory definitions 
Update for new member query_status_fence_gpu_mc_ptr in MESAPI_SET_HW_RESOURCES.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Le Ma
4842b9f3a7 drm/amdgpu/mes: update mes fw api 
Update mes_api_def.h to match the latest mes fw.

v2: clean up coding style based on kernel standards:
  - fix indentation and alignment
  - break long lines
  - put the opening brace last on the line
  - remove unnecessary blank line and space
  - replace uint(32|64) with standard uint(32|64)_t

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
shaoyunl
38d5bbef5d drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOV 
SMU firmware already been loaded from host, don't enable it for now.
May need to re-work it if we want to enable the SMU for guest in the future.

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
James Zhu
df3183b37a drm/amdgpu: fix typo for vcn3/jpeg3 idle check 
fix typo for vcn3/jpeg3 idle check

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Yong Zhao
3a2f0c813b drm/amdkfd: Support Sienna_Cichlid KFD v4 
v4: drop get_tile_config, comment out other callbacks

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:11 -04:00
Jerry (Fangzhi) Zuo
81d9bfb8c5 drm/amdgpu/dc: Add missing Sienna_Cichlid chip id 
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
689dede0a0 drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid 
Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
1f5d9cad08 drm/amdgpu: fix SDMA hdp flush engine conflict 
Each of HDP flush engine should be used by one ring, correct allocate of
hdp flush engine to SDMA ring.
Correct me value of each SDMA ring, as it was cleared when init microcode.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
98f8ea29ff drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid. 
Enable mmhub clockgating.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
bcc8367f94 drm/amd/amdgpu: add athub ls support 
athub ls is bounded with hdp ls,verified.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
3a32c25a8e drm/amd/amdgpu: add IH cg support 
IH cg verified

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
ca36461f42 drm/amd/amdgpu: add HDP mgcg and ls support 
add HDP mgcg and ls support and verified

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Kenneth Feng
91c6adf873 drm/amd/amdgpu: fix the HDP LS/DS/SD programming 
confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN
have to be set for SRAM LS/DS/SD

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
850e56ba44 drm/amdgpu: update golden setting for gfx10.3 
Update gfx golden setting for gfx10.3.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Leo Liu
d6b0185b8d drm/amdgpu: set the LMI ctrl and reset earlier 
So the LMI register will be programmed properly

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Leo Liu
07d8e891ff drm/amdgpu: fix the PSP front door loading VCN firmware 
for the second instance with correct index

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Leo Liu
14765e9c22 drm/amdgpu: change the offset for VCN FW cache window 
The signed header is added

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
00194def45 drm/amdgpu: open GFX clock gating for sienna_cichlid 
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
87ba7feafa drm/amdgpu: switch to query reserved fb size from vbios (v3) 
For Sienna_Cichlid, query fw_reserved_fb_size from vbios directly.
For navi1x, fall back to default 64K TMR size.
For pre-navi, no need to reserve tmr region in top LFB.

v2: fix TMR define (Alex)
v3: partially revert size change

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
9a244ebe81 drm/amdgpu: add atomfirmware helper funciton to query reserved fb size 
fw_reserved_size_in_kb is introduced for driver to query
the TMR region reserved by PSP BL in Sienna_Cichlid and onwards

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Likun Gao
738c822c7f drm/amdgpu: only send one sdma firmware for sienna_cichlid 
As all four sdma firmware are same, PSP only receive one SDMA fw.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
321b3eeb77 drm/amdgpu: drop gfx_v10_0_tiling_mode_table_init 
tiling mode table is not used anymore for gfx10

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:10 -04:00
Hawking Zhang
8b41903a2b drm/amdgpu: support query vram info for sienna_cichlid 
support query vram_module v11 and vram_info v2_5
for sienna_cichlid

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
f95c20464d drm/amdgpu: disable gfxoff for sienna_cichlid 
Temporary disable gfxoff for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
0f7ee05750 drm/amdgpu: add cp firmware backdoor loading triger 
Triger CP ucode addr and data to backdoor load CP firmware.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Hawking Zhang
305401e77b drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3 
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
263acd471f drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid 
Add gc golden setting for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
4d72dd12f0 drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid 
By adding JPEG HW block to Sienna_Cichlid

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b467c4f5b4 drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid 
By setting up the flags to the ASIC

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b52e271e15 drm/amdgpu: add Sienna_Cichlid JPEG PG and CG support 
This is for static powergating and clockgating

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
dfd57dbf44 drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid 
With basic IP block functions and ring functions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b8f10585cb drm/amdgpu: enable VCN3.0 for Sienna_Cichlid 
By adding VCN HW block to Sienna_Cichlid

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
265120abc0 drm/amdgpu: add Sienna_Cichlid VCN to the VCN family 
By adding Sienna_Cichlid VCN firmware

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
e823be13db drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid 
By setting up the flags to the ASIC

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
fedac0155a drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2) 
This is for static powergating and clockgating

v2: fix registers (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
cf14826cdf drm/amdgpu: add VCN3.0 support for Sienna_Cichlid 
With basic IP block functions and ring functions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
25fc05648f drm/amdgpu/mes: correct register offset for sienna_cichlid 
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00