Commit Graph

5 Commits

Author SHA1 Message Date
Cezary Rojewski
8ec7d60432 ASoC: Intel: haswell: Power transition refactor
Update D0 <-> D3 sequence to correctly transition hardware and DSP core
from and to D3. On top of that, set SHIM registers to their recommended
defaults during D0 and D3 proceduces as HW does not reset registers for
us.

Connected to:
[alsa-devel][BUG] bdw-rt5650 DSP boot timeout
https://mailman.alsa-project.org/pipermail/alsa-devel/2019-July/153098.html

Github issue ticket reference:
https://github.com/thesofproject/linux/pull/1842

Tested on:
- BDW-Y RVP with rt286
- SAMUS with rt5677

Proposed solution (both in July 2019 and on github):
'Revert "ASoC: Intel: Work around to fix HW d3 potential crash issue"'
is NAKed as it only covers the problem up and actually brings back the
undefined behavior: some registers (e.g.: APLLSE) are describing LPT
offsets rather than WPT ones. In consequence, during power-transitions
driver issues incorrect writes and leaves the regs of interest alone.

Existing patch - the non-revert - does not resolve the HW D3 issue at
all as it ignores the recommended sequence and does not initialize
hardware registers as expected. And thus, leaving things as are is also
unacceptable.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Tested-by: Ross Zwisler <zwisler@google.com>
Link: https://lore.kernel.org/r/20200330194520.13253-1-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-17 19:54:20 +01:00
Thomas Gleixner
1802d0beec treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:41 -07:00
Pierre-Louis Bossart
92beb0a269 ASoC: Intel: Haswell: fix endianness handling
Make all Sparse warnings go away by using le16/32_to_cpu.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-07-25 17:21:07 +01:00
Julia Lawall
93189ea425 ASoC: Intel: constify sst_block_ops structures
The sst_block_ops structure is never modified, and is thus declared as
const.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Jie Yang <yang.jie@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 17:38:54 +00:00
Jie Yang
ba57f68235 ASoC: Intel: create haswell folder and move haswell platform files in
Restructure the sound/soc/intel/ directory: create haswell folder, and
move haswell platform files here.

Signed-off-by: Jie Yang <yang.jie@intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-06 17:49:45 +01:00