The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Since i.MX7ULP B0 chip, SNVS module is moved into M4
domain, so remove it from Linux clock table.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There are HSRUN mode clock mux and divider in SCG1 module,
and SMC1 can control i.MX7ULP CPU to run in RUN mode or
HSRUN mode, the mode switch bits are actually a clock mux,
add these clocks for clock driver and dtb to use.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
