Denis Efremov
c9c13ba428
PCI: Add PCI_STD_NUM_BARS for the number of standard BARs
...
Code that iterates over all standard PCI BARs typically uses
PCI_STD_RESOURCE_END. However, that requires the unusual test
"i <= PCI_STD_RESOURCE_END" rather than something the typical
"i < PCI_STD_NUM_BARS".
Add a definition for PCI_STD_NUM_BARS and change loops to use the more
idiomatic C style to help avoid fencepost errors.
Link: https://lore.kernel.org/r/20190927234026.23342-1-efremov@linux.com
Link: https://lore.kernel.org/r/20190927234308.23935-1-efremov@linux.com
Link: https://lore.kernel.org/r/20190916204158.6889-3-efremov@linux.com
Signed-off-by: Denis Efremov <efremov@linux.com >
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com >
Acked-by: Sebastian Ott <sebott@linux.ibm.com > # arch/s390/
Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com > # video/fbdev/
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com > # pci/controller/dwc/
Acked-by: Jack Wang <jinpu.wang@cloud.ionos.com > # scsi/pm8001/
Acked-by: Martin K. Petersen <martin.petersen@oracle.com > # scsi/pm8001/
Acked-by: Ulf Hansson <ulf.hansson@linaro.org > # memstick/
2019-10-14 10:22:26 -05:00
Xiaowei Bao
fd5d16531a
PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driver
...
The layerscape PCIe controller have 4 BARs.
BAR0 and BAR1 are 32bit, BAR2 and BAR4 are 64bit and that's a
fixed hardware configuration.
Set the bar_fixed_64bit variable accordingly.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com >
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-14 10:48:10 +01:00
Kishon Vijay Abraham I
626961dd6d
PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
...
Add const qualifier to struct dw_pcie_ep_ops member of
struct dw_pcie_ep.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
2019-04-15 13:24:02 +01:00
Xiaowei Bao
a805770d8a
PCI: layerscape: Add EP mode support
...
Add the PCIe EP mode support to the layerscape platform controller.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Reviewed-by: Minghuan Lian <minghuan.lian@nxp.com >
Reviewed-by: Zhiqiang Hou <zhiqiang.hou@nxp.com >
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com >
2019-02-21 10:40:55 +00:00
