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10908 Commits

Author SHA1 Message Date
Jason A. Donenfeld
9285ec4c8b timekeeping: Use proper clock specifier names in functions 
This makes boot uniformly boottime and tai uniformly clocktai, to
address the remaining oversights.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20190621203249.3909-2-Jason@zx2c4.com
 2019-06-22 12:11:27 +02:00
Harry Wentland
6fbefb84a9 drm/amd/display: Add DC core changes for DCN2 
Core DC changes for DCN2.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:35 -05:00
Harry Wentland
7ed4e6352c drm/amd/display: Add DCN2 HW Sequencer and Resource 
Add DCN2 resource definition and HW Sequencer changes.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:35 -05:00
Harry Wentland
18eaea4bf8 drm/amd/display: Add DCN2 VMID 
Add support to program DCN2 VMID (Virtual Memory Support)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:35 -05:00
Harry Wentland
83421f32b7 drm/amd/display: Add DCN2 IPP 
Add support to program DCN2 cursor (IPP)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:35 -05:00
Harry Wentland
345429a67c drm/amd/display: Add DCN2 DWB 
Add support to program the DCN2 DWB (Display Writeback)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:35 -05:00
Harry Wentland
fa0d2c989c drm/amd/display: Add DCN2 MMHUBBUB 
Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
bbeb64d0eb drm/amd/display: Add DCN2 HUBP and HUBBUB 
Add support to program the DCN2 HUBP (Display to data fabric interface
pipe) and HUBBUB (DCN memory HUB interface)

HW Blocks:

 +--------++------+
 | HUBBUB || HUBP |
 +--------++------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
f7de96ee8b drm/amd/display: Add DCN2 DPP 
Add support to program the DCN2 DPP (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
f789b0b82b drm/amd/display: Add DCN2 MPC 
Add support to program the DCN2 MPC (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
eb7a74a36c drm/amd/display: Add DCN2 OPP 
Add support to program the DCN2 OPP (Output Plane Processing)

HW Blocks:

    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
2d78b3a177 drm/amd/display: Add DCN2 OPTC 
Add support for programming the DCN2 OPTC (Output Timing Controller)

HW Blocks:

    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
fcee01b9f8 drm/amd/display: Add DCN2 clk mgr 
Adds support for handling of clocking relevant to the DCN2 block,
including programming of the DCCG (Display Controller Clock Generator)
block:

HW Blocks:

    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
ca4d9b3a5a drm/amd/display: Add DCN2 DIO 
Add support for the DIO (Display IO)  block of DCN2, which entails our
stream and link encoders.

HW Blocks:

    +--------+
    |  DIO   |
    +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
728c06986a drm/amd/display: Add DCN2 changes to DML 
Update DML (Display Mode Lib) to support DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
bff65b7781 drm/amd/display: Add DCN2 IRQ handling 
Add support to program DCN2 IRQ handling

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
9647509497 drm/amd/display: Add DCN2 BIOS parsing 
Handle BIOS parsing for DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
2e35facf82 drm/amd/display: Add GPIO support for DCN2 
Adding support to program GPIO HW block of DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
38e7128960 drm/amd/display: add AUX and I2C for DCN2 
Adding support to program DCN2 AUX and I2C HW.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
9793014570 drm/amd/display: Add DCN2 and NV ASIC ID 
DCN2.0 (Display Core Next) is the display block in Navi10.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Xiaojie Yuan
76b743f45d drm/amd/display: use fixed-width data type for soc bounding box struct 
since it's firmware.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Leo Li
57b3ec35d5 drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h 
DC needs to include the soc bounding box when initializing HW resources.

Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is
required to define amdgpu_device. The solution here is to split the
bounding box structs into a different header, then include it in both
amdgpu_ucode.h, and relevant DC HW resource files.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
48321c3dde drm/amd/display: Read soc_bounding_box from gpu_info (v2) 
[WHY]
We don't want to expose sensitive ASIC information before ASIC release.

[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.

v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
hersen wu
edee92c379 drm/amd/powerplay: notify smu with active display count 
when dc update clocks via smu, smu needs to know how many
displays active. this interface is for dc notify number
of active displays to smu.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
hersen wu
5c170a59e7 drm/amd/powerplay: allow dc request uclk change 
when dc set mode or color format in frame buffer
change, it may request clock changes, like dispclk,
dcfclk, uclk. after smu get clock requests, smu
will make decision.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Hawking Zhang
ccbf007b47 drm/amdgpu: initialize THM & CLK IP registers base address 
was missed before.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Marek Olšák
61af800fe7 drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2) 
Proper size is 0.

v2: squash in whitespace fixes (Ernst Sjöstrand)

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Kevin Wang
93dfbcefb3 drm/amd/powerplay: remove unsupport function set_thermal_fan_table for navi10 
the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Jack Xiao
7c6fe84cf5 drm/amd/powerplay: enable BACO feature as WAR 
It would hit SMU fw bug without BACO enablement when audio
driver put audio device to D3 state. Before the bug in SMU fw
get fixed, enable BACO feature as WAR.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Kevin Wang
a39bf39816 drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabled 
the uclk dpm feature is not work well on all navi10 asic,
use pp feature mask module parameter to control it.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
tiancyin
4f56d9d412 drm/amdgpu: add new navi10 DIDs 
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
tiancyin
408e27cbba drm/amd/powerplay: add ppt interface version log 
Include the interface version as well.

Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Alex Deucher
6ad68a7e1f drm/amdgpu/gfx10: update to latest golden setting 
Fix UTCL1_CGTT_CLK_CTRL

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Alex Deucher
5917458548 drm/amdgpu/powerplay/vega20: use correct table index 
Use the SMU_* variant so we look up the correct index.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Leo Liu
450af30ce2 drm/amdgpu/VCN: enable indirect DPG SRAM mode 
This is default mode for VCN2.x now

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Leo Liu
dc8ae677c2 drm/amdgpu/VCN: implement indirect DPG SRAM mode 
SRAM will be programmed by PSP

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Leo Liu
a77b9fdf9a drm/amdgpu/VCN: add buffer for indirect SRAM usage 
This will be used later for indirect SRAM mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Jack Xiao
1768908ec5 drm/amd/powerplay: disable fw dstate when gfxoff is enabled 
SMU FW has bug that it would cause hung when both fw dstate and
gfxoff are enabled at the same time.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Jack Xiao
4bc920a680 drm/amd/powerplay: update smu11_driver_if_navi10.h 
update the smu11_driver_if_navi10.h since navi10 smu fw
update to 42.23

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Jack Xiao
86ddf3529e drm/amdgpu/psp: add new psp interface for vcn updating sram 
PSP leverages the existing fw loading function for vcn updating sram.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Jack Xiao
c76ff09bef drm/amdgpu/psp: convert ucode id to psp ucode id 
Convert ucode id to the corresponding psp ucode id.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Jack Xiao
6e72d8e9fb drm/amdgpu: add corresponding vcn ram ucode id 
Add VCN RAM ucode id in corresponding to psp ucode id.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Jack Xiao
68c0798cd9 drm/amdgpu/psp: add new VCN RAM ucode id to psp 
PSP supports to program vcn sram by ucode loading interface.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
157710ea4d drm/amdgpu: enable VCN2.0 DPG mode 
It will be the default for VCN2.x family

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
7282da0b3a drm/amdgpu/VCN2.0: add DPG pause mode 
Pause the DPG when not doing decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
bf4865b587 drm/amdgpu/VCN2.0: add DPG mode start and stop (v2) 
This is for using SRAM directly

v2: rebase (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
19c663fc77 drm/amdgpu/VCN2.0: add direct SRAM read and write 
This will be the basic and used for DPG mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
b3ef5ce037 drm/amdgpu/VCN2.0 remove unused Macro and declaration 
Just for cleanup

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Kevin Wang
0c83d32c56 drm/amd/powerplay: simplified od_settings for each asic 
the od_settings is asic related data, so move it to asic file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Kevin Wang
8f30a16d3a drm/amd/powerplay: move od_default_setting callback to asic file 
the set default od_setting is asic related function,
so move thic code to vega20_ppt file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00