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10908 Commits

Author SHA1 Message Date
Hawking Zhang
91d3130a4d drm/amdgpu: init gfx power gating on raven 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:41:02 -04:00
Hawking Zhang
6bce466710 drm/amdgpu/gfx9: rlc save&restore list programming 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:41:02 -04:00
Hawking Zhang
c9719c69ac drm/amdgpu/gfx9: add rlc bo init/fini 
setup the save and restore buffers used for gfx
powergating.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:41:01 -04:00
Hawking Zhang
e999e6e945 drm/amdgpu: correct gfx9 csb size 
programming pa_sc_raster_config/config1 reg is removed from gfx9 csb

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:41:00 -04:00
Hawking Zhang
f9d1b81d57 drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG 
Required for proper handshaking between the GFX and RLC.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:59 -04:00
Hawking Zhang
a4d41ad0ef drm/amdgpu/gfx9: extend rlc fw setup 
Required for gfx powergating.

Change-Id: I5a2f8f41253686d8bb776a92aa68bf90877ebaa8
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:58 -04:00
Huang Rui
a4dc61f574 drm/amdgpu: add gfx clock gating for raven 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:58 -04:00
Chunming Zhou
5cf7433d99 drm/amdgpu/gfx9: add raven gfx config 
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:57 -04:00
Chunming Zhou
eaa8572403 drm/amdgpu/gfx9: add chip name for raven when initializing microcode 
Fetch the correct ucode for raven.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:56 -04:00
Chunming Zhou
a5fdb3369a drm/amdgpu: add gc9.1 golden setting (v2) 
Add the GFX9 golden settings.

v2: squash in updates

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:55 -04:00
Chunming Zhou
060d124b06 drm/amdgpu: add module firmware for raven 
Fetch correct firmware for raven for gfx and sdma.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:54 -04:00
Chunming Zhou
4456ef4ea6 drm/amdgpu: add Raven chip id case for ucode 
Set the appropriate ucode loading mechanism.  Set to
direct for now.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:54 -04:00
Huang Rui
5c5928a238 drm/amdgpu: enable soc15 clock gating flags for raven 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:53 -04:00
Huang Rui
9e5a9eb4ff drm/amdgpu/soc15: add clock gating functions for raven 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:52 -04:00
Hawking Zhang
957c6fe188 drm/amd/amdgpu: fill in raven case in soc15 early init 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:51 -04:00
Chunming Zhou
e0ab957868 drm/amdgpu/soc15: add Raven golden setting 
Add the common golden settings for Raven.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:50 -04:00
Chunming Zhou
1023b797d1 drm/amdgpu: add Raven ip blocks (v2) 
Add the IP blocks for RAVEN.

v2: drop DC for upstream (Alex)

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:50 -04:00
Chunming Zhou
2ca8a5d2eb drm/amdgpu: add RAVEN family id definition 
RAVEN is a new APU.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:49 -04:00
Alex Deucher
702f9292ad drm/amdgpu: add register headers for VCN 1.0 
Add registers for Video Controller Next 1.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:48 -04:00
Alex Deucher
bfd86c1ab3 drm/amdgpu: add register headers for THM 10.0 
Add registers for THerMal control 10.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:47 -04:00
Alex Deucher
ce869c637e drm/amdgpu: add register headers for SDMA 4.1 
Add registers for SDMA 4.1

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:46 -04:00
Alex Deucher
c4dc7b1a54 drm/amdgpu: add register headers for NBIO 7.0 
Add registers for NBIO 7.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:45 -04:00
Alex Deucher
cfeb9192fe drm/amdgpu: add register headers for MP 10.0 
Add registers for MP 10.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:44 -04:00
Alex Deucher
96ded7747c drm/amdgpu: add register headers for MMHUB 9.1 
Add registers for the MultiMedia Hub 9.1

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:44 -04:00
Alex Deucher
7582d7e649 drm/amdgpu: add register headers for GC 9.1 
Registers for Graphics Controller 9.1

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:43 -04:00
Alex Deucher
752ca077d5 drm/amdgpu: add register headers for DCN 1.0 
Registers for Display Controller Next 1.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:42 -04:00
Monk Liu
4f059ecdce drm/amdgpu:use job's list instead of check fence 
because if the fence is really signaled, it could already
released so the fence pointer is a wild pointer, but if
we use job->base.node we are safe because job will not
be released untill amdgpu_job_timedout finished.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:41 -04:00
Monk Liu
65781c78ad drm/amdgpu/SRIOV:implement guilty job TDR for(V2) 
1,TDR will kickout guilty job if it hang exceed the threshold
of the given one from kernel paramter "job_hang_limit", that
way a bad command stream will not infinitly cause GPU hang.

by default this threshold is 1 so a job will be kicked out
after it hang.

2,if a job timeout TDR routine will not reset all sched/ring,
instead if will only reset on the givn one which is indicated
by @job of amdgpu_sriov_gpu_reset, that way we don't need to
reset and recover each sched/ring if we already know which job
cause GPU hang.

3,unblock sriov_gpu_reset for AI family.

V2:
1:put kickout guilty job after sched parked.
2:since parking scheduler prior to kickout already occupies a
while, we can do last check on the in question job before
doing hw_reset.

TODO:
1:when a job is considered as guilty, we should mark some flag
in its fence status flag, and let UMD side aware that this
fence signaling is not due to job complete but job hang.

2:if gpu reset cause all video memory lost, we need introduce
a new policy to implement TDR, like drop all jobs not yet
signaled, and all IOCTL on this device will return ERROR
DEVICE_LOST.
this will be implemented later.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:40 -04:00
Monk Liu
75fbed20e5 drm/amdgpu:don't init entity for KIQ 
We don't need a scheduler for KIQ.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:39 -04:00
Monk Liu
0c63e11340 drm/amdgpu:only call flr_work under infinite timeout 
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:39 -04:00
Monk Liu
7225f8736c drm/amdgpu:use job* to replace voluntary 
that way we can know which job cause hang and
can do per sched reset/recovery instead of all
sched.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:38 -04:00
Monk Liu
4fbf87e2fe drm/amdgpu:don't invoke srio-gpu-reset in gpu-reset (v2) 
because we don't want to do sriov-gpu-reset under certain
cases, so just split those two funtion and don't invoke
sr-iov one from bare-metal one.

V2:
remove debugfs_gpu_reset routine on SRIOV case.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:37 -04:00
Chunming Zhou
bea396726d drm/amdgpu: id reset count only is updated when used end v2 
before that, we have function to check if reset happens by using reset count.
v2: always update reset count after vm flush

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:36 -04:00
Chunming Zhou
b9bf33d5ac drm/amdgpu: make pipeline sync be in same place v2 
v2: directly return for 'if' case.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:35 -04:00
Chunming Zhou
df83d1ebc9 drm/amdgpu: add sched sync for amdgpu job v2 
this is an improvement for previous patch, the sched_sync is to store fence
that could be skipped as scheduled, when job is executed, we didn't need
pipeline_sync if all fences in sched_sync are signalled, otherwise insert
pipeline_sync still.

v2: handle error when adding fence to sync failed.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> (v1)
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:35 -04:00
Christian König
a022c54e60 drm/amdgpu: remove unsed amdgpu_gem_handle_lockup (v2) 
This kind of reset handling was removed a long time ago.

v2: fix warning (Alex)

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:34 -04:00
Chunming Zhou
6643be65d9 drm/amdgpu: print when gpu reset successed 
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Roger.He <Hongbo.He@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:33 -04:00
Chunming Zhou
fcf0649fcc drm/amdgpu: fix ring0 failed on pro card 
the root cause is vram content is lost completely after pci reset.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Roger.He <Hongbo.He@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:32 -04:00
Roger.He
738f64ccc2 drm/amdgpu: extend lock range for race condition when gpu reset 
to cover below case:
1. A task gart bind/unbind but not add to adev->gtt_list yet
2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roger.He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:31 -04:00
Alex Xie
455a7bc27c drm/amdgpu: Fix comments in source code 
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:31 -04:00
Alex Xie
ea81a173ff drm/amdgpu: fix errors in comments. 
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:30 -04:00
Alex Deucher
67fb56a6dd drm/amdgpu/gfx9: move define to header file 
rather than defining it locally.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:29 -04:00
Nikola Pajkovsky
5b9c58f997 drm/amd/amdgpu: get rid of else branch 
else branch is pointless if it's right at the end of function and use
unlikely() on err path.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nikola Pajkovsky <npajkovsky@suse.cz>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:28 -04:00
Monk Liu
503bb31be4 drm/amdgpu:cleanup flag not used 
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:27 -04:00
Monk Liu
3b4d68e993 drm/amdgpu:use FRAME_CNTL for new GFX ucode (v2) 
AI affected:

CP/HW team requires KMD insert FRAME_CONTROL(end) after
the last IB and before the fence of this DMAframe.

this is to make sure the cache are flushed, and it's a must
change no matter MCBP/SR-IOV or bare-metal case because new
CP hw won't do the cache flush for each IB anymore, it just
leaves it to KMD now.

with this patch, certain MCBP hang issue when rendering
vulkan/chained-ib are resolved.

v2: drop gfx8 changes.  gfx8 is not affected (Alex)

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:26 -04:00
Monk Liu
d951eeddfa drm/amdgpu:new PM4 entry for VI/AI 
TMZ package will be used for VULKAN/CHAINED-IB MCBP

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:26 -04:00
Monk Liu
635e713298 drm/amdgpu:change SR-IOV DMAframe scheme 
According to CP/hw team requirment, to support PAL/CHAINED-IB
MCBP, kernel driver must guarantee DE_META must be inserted
right prior to the work_load DE IB (with PREEMPT flag), there
cannot be any non-work_load DE IB between-in DE_META and
work_load DE IB.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:25 -04:00
Monk Liu
9524354358 drm/amdgpu:unify gfx8/9 ce/de meta_data 
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:24 -04:00
Monk Liu
eaa05d5288 drm/amdgpu:cleanup indent/format for gfx_v9_0.c 
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:23 -04:00
Frank Min
b48622b088 drm/amdgpu: clean doorbell after sending init table to mmsch 
According to HW design, need to clean doorbell after setup MMSCH
table.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-05-24 17:40:22 -04:00