Use the functions introduced in by the previous patch,
suspend_device_irqs(), resume_device_irqs() and check_wakeup_irqs(),
to rework the handling of interrupts during suspend (hibernation) and
resume. Namely, interrupts will only be disabled on the CPU right
before suspending sysdevs, while device drivers will be prevented
from receiving interrupts, with the help of the new helper function,
before their "late" suspend callbacks run (and analogously during
resume).
In addition, since the device interrups are now disabled before the
CPU has turned all interrupts off and the CPU will ACK the interrupts
setting the IRQ_PENDING bit for them, check in sysdev_suspend() if
any wake-up interrupts are pending and abort suspend if that's the
case.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Ingo Molnar <mingo@elte.hu>
* 'x86-stage-3-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (190 commits)
Revert "cpuacct: reduce one NULL check in fast-path"
Revert "x86: don't compile vsmp_64 for 32bit"
x86: Correct behaviour of irq affinity
x86: early_ioremap_init(), use __fix_to_virt(), because we are sure it's safe
x86: use default_cpu_mask_to_apicid for 64bit
x86: fix set_extra_move_desc calling
x86, PAT, PCI: Change vma prot in pci_mmap to reflect inherited prot
x86/dmi: fix dmi_alloc() section mismatches
x86: e820 fix various signedness issues in setup.c and e820.c
x86: apic/io_apic.c define msi_ir_chip and ir_ioapic_chip all the time
x86: irq.c keep CONFIG_X86_LOCAL_APIC interrupts together
x86: irq.c use same path for show_interrupts
x86: cpu/cpu.h cleanup
x86: Fix a couple of sparse warnings in arch/x86/kernel/apic/io_apic.c
Revert "x86: create a non-zero sized bm_pte only when needed"
x86: pci-nommu.c cleanup
x86: io_delay.c cleanup
x86: rtc.c cleanup
x86: i8253 cleanup
x86: kdebugfs.c cleanup
...
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (21 commits)
MIPS: Alchemy: PB1200: use SMC91X platform data.
MIPS: Alchemy: MIPS hazard workarounds are not required.
MIPS: Alchemy: provide cpu feature overrides.
MIPS: Alchemy: unify CPU model constants.
MIPS: Make a needlessly global symbol static in arch/mips/kernel/smp.c
MIPS: Fix global namespace pollution in arch/mips/kernel/smp-up.c
MIPS: Malta: make a needlessly global integer variable static
MIPS: Use BUG_ON() where possible.
MIPS: Convert obsolete irq_desc_t to struct irq_desc
MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms
MIPS: EMMA2RH: Set UART mapbase
MIPS: EMMA2RH: Use set_irq_chip_and_handler_name
MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts
MIPS: Mark Eins: Fix cascading interrupt dispatcher
MIPS: Au1000: convert to using gpiolib
MIPS: Stop using <asm-generic/int-l64.h>.
MIPS: Cavium: Add -Werror
MIPS: Makefile: Add simple make install target.
MIPS: Compat: Zero upper 32-bit of offset_high and offset_low.
MIPS: __raw_spin_lock() may spin forever on ticket wrap.
...
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (180 commits)
powerpc: clean up ssi.txt, add definition for fsl,ssi-asynchronous
powerpc/85xx: Add support for the "socrates" board (MPC8544).
powerpc: Fix bugs introduced by sysfs changes
powerpc: Sanitize stack pointer in signal handling code
powerpc: Add write barrier before enabling DTL flags
powerpc/83xx: Update ranges in gianfar node to match other dts
powerpc/86xx: Move gianfar mdio nodes under the ethernet nodes
powerpc/85xx: Move gianfar mdio nodes under the ethernet nodes
powerpc/83xx: Move gianfar mdio nodes under the ethernet nodes
powerpc/83xx: Add power management support for MPC837x boards
powerpc/mm: Introduce early_init_mmu() on 64-bit
powerpc/mm: Add option for non-atomic PTE updates to ppc64
powerpc/mm: Fix printk type warning in mmu_context_nohash
powerpc/mm: Rename arch/powerpc/kernel/mmap.c to mmap_64.c
powerpc/mm: Merge various PTE bits and accessors definitions
powerpc/mm: Tweak PTE bit combination definitions
powerpc/cell: Fix iommu exception reporting
powerpc/mm: e300c2/c3/c4 TLB errata workaround
powerpc/mm: Used free register to save a few cycles in SW TLB miss handling
powerpc/mm: Remove unused register usage in SW TLB miss handling
...
* git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6: (70 commits)
ide: keep track of number of bytes instead of sectors in struct ide_cmd
ide: remove ide_execute_pkt_cmd() (v2)
ide: add ->dma_timer_expiry method and remove ->dma_exec_cmd one (v2)
ide: set hwif->expiry prior to calling [__]ide_set_handler()
ide: use do_rw_taskfile() for ATA_CMD_PACKET commands
ide: pass command to ide_map_sg()
ide: remove ide_end_request()
ide: use ide_end_rq() in ide_complete_rq()
ide: pass number of bytes to complete to ide_complete_rq()
ide: remove BUG() from ide_complete_rq()
ide: move rq->errors quirk out from ide_end_request()
ide: pass error value to ide_complete_rq()
ide: sanitize ide_end_rq()
ide: add ide_end_rq() (v2)
ide: make ide_special_rq() BUG() on unknown requests
ide: sanitize ide_finish_cmd()
ide: use ide_complete_cmd() for REQ_UNPARK_HEADS
ide: use ide_complete_cmd() for head unload commands
ide: task_error() -> task_error_cmd()
ide: unify exit paths in task_pio_intr()
...
Some Phytec cameras have a I2C GPIO expander which allows it to
switch between different sensor bus widths. This was previously
handled in the camera driver. Since handling of this switch
varies on several boards the cameras are used on, the board
support seems a better place to handle the switch
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
All soc-camera camera and host drivers must specify supported data signal
polarity, after all drivers are fixed, we'll add a suitable test to
soc_camera_bus_param_compatible().
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Add platform data for the smc91x on the PB1200/DB1200, and remove the
now unused AU1X00 entry in smc91x.h.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
The Alchemy manuals state:
"All pipeline hazards and dependencies are enforced by hardware interlocks
so that any sequence of instructions is guaranteed to execute correctly.
Therefore, it is not necessary to pad legacy MIPS hazards (such as
load delay slots and coprocessor accesses) with NOPs."
Run-tested on Au12x0, without any ill effects.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add cpu feature override constants tailored for all Alchemy variants
currently in existence.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
create mode 100644 arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
This patch removes the various CPU_AU1??? model constants in favor of
a single CPU_ALCHEMY one.
All currently existing Alchemy models are identical in terms of cpu
core and cache size/organization. The parts of the mips kernel which
need to know the exact CPU revision extract it from the c0_prid register
already; and finally nothing else in-tree depends on those any more.
Should a new variant with slightly different "company options" and/or
"processor revision" bits in c0_prid appear, it will be supported
immediately (minus an exact model string in cpuinfo).
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The variable cpu_callin_map is needlessly defined global, so let's
make it static now.
Build-tested using malta_defconfig.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The following symbols in arch/mips/kernel/smp-up.c are needlessly
defined global:
up_send_ipi_single()
up_init_secondary()
up_smp_finish()
up_cpus_done()
up_boot_secondary()
up_smp_setup()
up_prepare_cpus()
This patch makes the symbols static.
Build-tested using malta_defconfig.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The variable `mips_revision_corid' is needlessly defined global in
arch/mips/mti-malta/malta-init.c, and this patch makes it static.
Build-tested with malta_defconfig.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Impact: cleanup
Convert the last remaining users to struct irq_desc.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fix two remaining set_irq_chip_and_handler() users which are encourated
to migrate to set_irq_chip_and_handler_name().
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
EMMA's GPIO interrupts are latched by GPIO interrupt status register.
In this case, we're encouraged to use handle_edge_irq() handler.
The following changes are made along with replacing set_irq_chip() with
set_irq_chip_and_handler_name(,,handle_edge_irq,"edge"):
* Fix emma2rh_gpio_irq_ack not to disable interrupts
With handle_edge_irq(), we're not expected to disable interrupts
when chip->ack is served, so fix it accordingly. We also add a new
emma2rh_gpio_irq_mask_ack() for chip->mask_ack operation, instead.
* Remove emma2rh_gpio_irq_end(), as chip->end is no longer served.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch converts the GPIO board code to use gpiolib.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Through sys_llseek() arguably should do exactly that it doesn't which
means llseek(2) will fail for o32 processes if offset_low has bit 31 set.
As suggested by Heiko Carstens.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
If the lock is not acquired and has to spin *and* the second attempt
to acquire the lock fails, the delay time is not masked by the ticket
range mask. If the ticket number wraps around to zero, the result is
that the lock sampling delay is essentially infinite (due to casting
-1 to an unsigned int).
The fix: Always mask the difference between my_ticket and the current
ticket value before calculating the delay.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Impact: cleanup
It's unused, since about 1995. So remove all initialization of it in
preparation for actually removing the field.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Everyone defines it, and only one person uses it
(arch/mips/sgi-ip27/ip27-nmi.c). So just open code it there.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Cc: linux-mips@linux-mips.org
Impact: cleanup
This patch allow us to use KVM hypercalls
Signed-off-by: Matias Zabaljauregui <zabaljauregui at gmail.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Impact: intermittent guest segv/crash fix
I've been seeing random guest bad address crashes and segmentation faults:
bisect led to 4f98a2fee8 (vmscan: split LRU lists into anon & file sets),
but that's a red herring.
It turns out that lguest never hooked up the pte_update/pte_update_defer
calls, so our ptes were not always in sync. After the vmscan commit, the
bug became reproducible; now a fsck in a 64MB guest causes reproducible
pagetable corruption.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Cc: jeremy@xensource.com
Cc: virtualization@lists.osdl.org
Cc: stable@kernel.org
Modern versions of gcc have a better range of ColdFire optimization
switches for the vairous ColdFire family members. Use these when we can.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Hypervisor versions older than version 1.6.1 cannot handle
leaving the profile counter overflow interrupt chirping
when the system does a soft reset.
So use a reboot notifier to shut off the NMI watchdog.
Signed-off-by: David S. Miller <davem@davemloft.net>
I get random oopses on my Kirkwood board at startup when L2 cache is
enabled. FYI I'm using Marvell uboot version 3.4.16
Each boot produces the same oops, but anything that changes the kernel
size (even only changing initramfs) makes the oops different.
I noticed that nothing invalidates the L2 cache before enabling it,
doing so fixes my problem.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Impact: ACPI 3 spec compliance, BIOS bug workaround
The ACPI 3 spec added another field to the E820 buffer -- which is
backwards incompatible, since it contains a validity bit.
Furthermore, there has been at least one report of a BIOS which
assumes that the buffer it is pointed at is the same buffer as for the
previous E820 call. Therefore, read the data into a temporary buffer
and copy the standard part of it if and only if the valid bit is set.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Impact: BIOS bugproofing
Since there are BIOSes known to clobber %ebx and %esi for INT 15 E820,
assume there is something out there clobbering %edi and/or %ebp too,
and don't wait for it to fail.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
