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52550 Commits

Author SHA1 Message Date
Chris Wilson
0ce611c906 drm/i915/dp: Fix inconsistent indenting 
Always show the FEC capability as it is initialised to 0 before error.
Fixing,

drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn: inconsistent indenting

Fixes: 08cadae8e1 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181120202439.13017-2-chris@chris-wilson.co.uk
 2018-12-04 09:32:57 +00:00
Jernej Skrabec
97f2930f5b drm/sun4i: Add compatible for H6 display engine 
H6 is first Allwinner SoC which supports 10 bit colors, HDR and AFBC.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-9-jernej.skrabec@siol.net
 2018-12-04 08:46:28 +01:00
Andrzej Hajda
67fbf3a3ef drm/exynos/iommu: merge IOMMU and DMA code 
As DMA code is the only user of IOMMU code both files can be merged.
It allows to remove stub functions, after slight adjustment of
exynos_drm_register_dma. Since IOMMU functions are used locally they
can be marked static.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
 2018-12-04 13:23:17 +09:00
Andrzej Hajda
39f6936843 drm/exynos/iommu: replace preprocessor conditionals with C conditionals 
Using C conditionals is preferred solution - it provides better code
coverage, makes code more clear.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
 2018-12-04 13:23:17 +09:00
Andrzej Hajda
a0b68a710b drm/exynos/iommu: move IOMMU specific stuff into exynos_drm_iommu.c 
Since __exynos_iommu* functions are used only in exynos_drm_iommu.c we can
move them there.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
 2018-12-04 13:23:17 +09:00
Andrzej Hajda
237556962e drm/exynos/iommu: integrate IOMMU/DMA internal API 
Exynos DRM drivers should work with and without IOMMU. Providing common
API generic to both scenarios should make code cleaner and allow further
code improvements.
The patch removes including of exynos_drm_iommu.h as the file contains
mostly IOMMU specific stuff, instead it exposes exynos_drm_*_dma functions
and puts them into exynos_drm_dma.c.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
 2018-12-04 13:23:17 +09:00
Andrzej Hajda
69908ed258 drm/exynos/iommu: remove DRM_EXYNOS_IOMMU Kconfig symbol 
DRM_EXYNOS_IOMMU symbol is not configurable, it is always equal to
EXYNOS_IOMMU.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
 2018-12-04 13:23:17 +09:00
Andrzej Hajda
29cbf24a4d drm/exynos: simplify DMA mapping 
Moving DMA mapping creation to drm_iommu_attach_device allows to avoid
looping through all components and maintaining DMA device flags.

v2: take care of configurations without IOMMU

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
 2018-12-04 13:23:17 +09:00
José Roberto de Souza
d53db442db drm/i915: Move display device info capabilities to its own struct 
This helps separate what capabilities are display capabilities.

v3: Moving display struct right after flags (Lucas)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130232048.14216-2-jose.souza@intel.com
 2018-12-03 14:55:41 -08:00
José Roberto de Souza
e1bf094b3c drm/i915: Add HAS_DISPLAY() and use it 
Right now it is decided if GEN has display by checking the num_pipes,
so lets make it explicit and use a macro.

Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130232048.14216-1-jose.souza@intel.com
 2018-12-03 14:55:39 -08:00
Olof Johansson
202f9977b0 Merge tag 'qcom-drivers-for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers 
Qualcomm ARM Based Driver Updates for v4.21

* Fix llcc license, includes, and error checks
* Remove use of memcpy in cmd-db and fix API breakage
* Add QCS404 compatible to SMD-RPM
* Minor fixes for QMI
* Add irq clear handling in QCOM Geni SE during init

* tag 'qcom-drivers-for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  drm: msm: Check cmd_db_read_aux_data() for failure
  soc: qcom: smd-rpm: Add QCS404 compatible
  soc: qcom: llcc-slice: Remove duplicated include from llcc-slice.c
  soc: qcom: cmd-db: Stop memcpy()ing in cmd_db_read_aux_data()
  soc: qcom: cmd-db: Remove memcpy()ing from cmd_db_get_header()
  soc: qcom: Drop help text for QCOM_QMI_HELPERS
  soc: qcom: qmi_interface: Limit txn ids to U16_MAX
  soc: qcom: llcc-slice: Add error checks for API functions
  soc: qcom/llcc: add MODULE_LICENSE tag
  soc: qcom: Add irq clear handling during SE init

Signed-off-by: Olof Johansson <olof@lixom.net>
 2018-12-03 13:10:10 -08:00
Manasi Navare
ae9e7ced4f drm/i915/dp: Fix link compute m_n calc for DSC 
Fix the intel_link_compute_m_n in case of display stream
compression. This patch passes the compressed_bpp to
intel_link_compute_m_n if compression is enabled.

Fixes: a4a157777c ("drm/i915/dp: Compute DSC pipe config in atomic check")
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181201010412.32372-1-manasi.d.navare@intel.com
 2018-12-03 11:52:27 -08:00
Eric Anholt
55a9b74846 drm/v3d: Add more tracepoints for V3D GPU rendering. 
The core scheduler tells us when the job is pushed to the scheduler's
queue, and I had the job_run functions saying when they actually queue
the job to the hardware.  By adding tracepoints for the very top of
the ioctls and the IRQs signaling job completion, "perf record -a -e
v3d:.\* -e gpu_scheduler:.\* <job>; perf script" gets you a pretty
decent timeline.

Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181201005759.28093-5-eric@anholt.net
Reviewed-by: Dave Emett <david.emett@broadcom.com>
 2018-12-03 11:26:23 -08:00
Eric Anholt
db176f6ba1 drm/v3d: Add missing fence timeline name for TFU. 
We shouldn't be returning v3d-render for our new queue.

Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 83d5139982db ("drm/v3d: Add support for submitting jobs to the TFU.")
Link: https://patchwork.freedesktop.org/patch/msgid/20181201005759.28093-6-eric@anholt.net
Reviewed-by: Dave Emett <david.emett@broadcom.com>
 2018-12-03 11:24:58 -08:00
Christian König
86bbd89d5d drm/syncobj: use dma_fence_get_stub 
Extract of useful code from the timeline work. Let's use just a single
stub fence instance instead of allocating a new one all the time.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Link: https://patchwork.freedesktop.org/patch/265248/
 2018-12-03 17:40:25 +01:00
Evan Quan
106ea7feb9 drm/amd/powerplay: support SoftMin/Max setting for some specific DPM 
For some case, no need to force SoftMin/Max settings for all DPMs.
It's OK to force on some specific DPM only.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:40:21 -05:00
Evan Quan
10cb3e6b63 drm/amd/powerplay: issue pre-display settings for display change event 
For display config change event only, pre-display config settings are
needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:40:20 -05:00
Evan Quan
f02be8279a drm/amd/powerplay: support new pptable upload on Vega20 
New pptable upload through sysfs interface is supported.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:40:20 -05:00
Alex Deucher
b52b6738cc drm/amdgpu/gmc8: always load MC firmware in the driver 
Some power features rely on the driver loaded version so always
load the MC firmware from the driver even if the vbios loaded
a version already.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2018-12-03 11:40:14 -05:00
Alex Deucher
a81a7c9c9e drm/amdgpu/gmc8: update MC firmware for polaris 
Some variants require different MC firmware images.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2018-12-03 11:40:01 -05:00
Jani Nikula
e1215de823 drm/i915/sysfs: make attrs arrays const 
They don't need to be modified.

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181004143750.30880-2-jani.nikula@intel.com
 2018-12-03 18:18:20 +02:00
Andrey Grodzovsky
d4535e2c01 drm/amdgpu: Implement concurrent asic reset for XGMI. 
Use per hive wq to concurrently send reset commands to all nodes
in the hive.

v2:
Switch to system_highpri_wq after dropping dedicated queue.
Fix non XGMI code path KASAN error.
Stop  the hive reset for each node loop if there
is a reset failure on any of the nodes.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:15:14 -05:00
Andrey Grodzovsky
a82400b57a drm/amdgpu: Handle xgmi device removal. 
XGMI hive has some resources allocted on device init which
needs to be deallocated when the device is unregistered.

v2: Remove creation of dedicated wq for XGMI hive reset.
v3: Use the gmc.xgmi.supported flag

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:15:08 -05:00
Andrey Grodzovsky
38cd8a280d drm/amdgpu/psp: Update waiting in psp mode1 reset. 
No point in use mdelay unless running from interrupt context (which we are not)
This is busy wait which will block the CPU for the entirety of the wait time.
Also, reduce wait time to 500ms as it is done in refernce code because
1s might cause PSP FW TO issues during XGMI hive reset.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:15:00 -05:00
Christian König
30da7bb184 drm/amdgpu: add missing error handling 
We ignored the return code here.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:14:54 -05:00
Christian König
1245adf315 drm/amdgpu: remove amdgpu_bo_backup_to_shadow 
It is unused.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:14:48 -05:00
Alex Deucher
47622ba033 drm/amdgpu: add a xgmi supported flag 
Use this to track whether an asic supports xgmi rather than
checking the asic type everywhere.

Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-12-03 11:14:39 -05:00
Chris Wilson
46592892e1 drm/i915/vgpu: Disallow loading on old vGPU hosts 
Since commit fd8526e509 ("drm/i915/execlists: Trust the CSB") we
actually broke the force-mmio mode for our execlists implementation. No
one noticed, so ergo no one is actually using an old vGPU host (where we
required the older method) and so can simply remove the broken support.

v2: csb_read can go as well (Mika)

Reported-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Fixes: fd8526e509 ("drm/i915/execlists: Trust the CSB")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130125954.11924-1-chris@chris-wilson.co.uk
 2018-12-03 16:08:26 +00:00
Alex Gonzalez
4fb86404a9 drm/panel: simple: Add AUO G101EVN010 panel support 
The change adds support for the AU Optronics G101EVN010 10.1" TFT LCD
panel.

Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
Reviewed-by: Rob Herring <robh@kernel.org>
[treding@nvidia.com: sort new entry alphabetically]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1540480173-12009-2-git-send-email-alex.gonzalez@digi.com
 2018-12-03 17:04:48 +01:00
Thierry Reding
8e2988a76c drm/tegra: sor: Support for audio over HDMI 
This code is very similar to the audio over HDMI support on older chips.
Interoperation with the audio codec is done via a pair of codec scratch
registers and an interrupt that is raised at the SOR when the codec has
written those registers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
 2018-12-03 16:37:26 +01:00
Junwei Zhang
d7fd67653f drm/amdgpu: update mc firmware image for polaris12 variants 
Some new variants require updated firmware.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2018-12-03 09:55:52 -05:00
Chris Wilson
26af893184 drm/i915/breadcrumbs: Reduce missed-breadcrumb false positive rate 
Change the on-cpu check to on-runqueue to catch if the waiter has been
woken (and reset its current_state back to TASK_UNINTERRUPTIBLE to
perform the seqno check) but is sleeping due to being preempted off the
cpu.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181203113701.12106-1-chris@chris-wilson.co.uk
 2018-12-03 14:34:08 +00:00
Jani Nikula
949fc52af1 drm/i915/icl: add pll mapping for DSI 
Add encoder specific pll mapping for DSI. The differences with the DDI
version are big enough to warrant a separate function.

v2: add posting read (Madhav)

Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181203094326.28294-1-jani.nikula@intel.com
 2018-12-03 15:55:27 +02:00
Madhav Chauhan
1026bea003 drm/i915/icl: Ungate DSI clocks 
Ungate the clocks on the selected port.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2a01b3158feda624f98581b780854fe3df8c328d.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:55:19 +02:00
Madhav Chauhan
32250c8e0e drm/i915/icl: Gate clocks for DSI 
As per BSPEC, depending on the DSI transcoder being used,
DDI clock for the associated port should be gated. This
patch does the same.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e032bc3d8fff91b8c2631c73121268214615a7e8.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:55:15 +02:00
Jani Nikula
690c318ed8 drm/i915/icl: add dummy DSI GPIO element execution function 
Add dummy debug logging GPIO element execution function for ICL.

Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f59009ea0a0ebc489a5ec66f387d9dcf7264141f.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:55:01 +02:00
Madhav Chauhan
56b7b1aa13 drm/i915/icl: Define display GPIO pins for DSI 
Display Pins are the only GPIOs that need to be used by
driver for DSI panels. So driver should now have its own
implementation to toggle these pins based on GPIO info
received from VBT sequences.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e7e3bb05d4f48b1876169a69f495bcf6d511fda5.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:51 +02:00
Madhav Chauhan
f4ff212030 drm/i915/icl: Define Panel power ctrl register 
There are two panel power sequencers. Each register
has two addressable instances. This patch defines
both the instances of Panel power control register

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/99bb687b17a9165527a6210a79271c8175c8a4e3.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:49 +02:00
Madhav Chauhan
05f2f03dd2 drm/i915/icl: Define missing bitfield for shortplug reg 
This patch define missing bitfield for shortplug ctl ddi
register which will be used for ICL DSI GPIO programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4b9feb75eb6c303556b91c8a23c505a4593a99a1.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:46 +02:00
Madhav Chauhan
2eae5d6bfa drm/i915/icl: Get pipe timings for DSI 
Transcoder timings for Gen11 DSI encoder
is available at pipe level unlike in older platform
where port specific registers need to be accessed.

v2 by Jani:
 - get timings for (!dsi || icl) instead of (dsi && icl).

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f60e0c1aee08248e758da3219d3239898b43ba41.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:44 +02:00
Madhav Chauhan
2ca711caec drm/i915/icl: Consider DSI for getting transcoder state 
For Gen11 DSI, we use similar registers like for eDP
to find if DSI encoder is connected or not to a pipe.
This patch refactors existing hsw_get_transcoder_state()
to handle this.

v2 by Jani:
 - Add WARN_ON(dsi && edp) (Ville)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2e10b977dfc7aa985a8559d6cd59ed0981848e95.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:33 +02:00
Madhav Chauhan
5a8507b5aa drm/i915/icl: Configure DSI Dual link mode 
This patch configures DSI video mode dual link by
programming DSS_CTL registers.

v2: Use new bitfield definitions from Anusha's patch
    Correct register to be programmed and use max
    depth buffer value (James)

v3 by Jani:
 - checkpatch fixes

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/d8962f4e1beffc2099b8bef8cb5a5191aa1d9efd.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:30 +02:00
Madhav Chauhan
d04afb1501 drm/i915/icl: Add DSI encoder compute config hook 
This patch implements compute config for Gen11 DSI encoder which is
required at the time of modeset.

For DSI 8X clock is AFE clock which is 5 times port clock.

v2 by Jani:
 - drop the enable nop hook
 - fixed_mode is always true
 - HAS_GMCH_DISPLAY() is always false

v3 by Jani:
 - set encoder->compute_config dropped during rebase

v4 by Jani:
 - squash Vandita's port clock patch
 - remove todo comment

Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a21574173caa5e2932d9e3c537b0931097ab5ac2.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:25 +02:00
Madhav Chauhan
ab8411483a drm/i915/icl: Get HW state for DSI encoder 
This patch read out the current hw state for DSI and
return true if encoder is active.

v2 by Jani:
 - Squash connector get hw state hook here
 - Squash encode get hw state fix here

v3 by Jani:
 - Add encoder->get_power_domains() (Imre)

v4 by Jani:
 - Make encoder->get_power_domains() sensible... (Imre)

v5 by Jani:
 - Power domains are bit positions, not bits (Stan, Imre)

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ec6da32a55b9fb045527f14e41ed3dce86d46a97.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:21 +02:00
Vandita Kulkarni
8327af281d drm/i915/icl: Add get config functionality for DSI 
This patch implements the functionality for getting PIPE configuration
to which DSI encoder is connected. Use the same method to get port clock
like other DDI encoders. Used during the atomic modeset.

v2 by Jani:
- Squash Madhav's and Vandita's get config bits together
- Move cnl_calc_wrpll_link() to intel_drv.h
- Drop extra temp variables
- Use enc_to_intel_dsi() instead of open coding

Co-developed-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f21fa4258068d04582f2bf30735e5536a8043bdf.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:16 +02:00
Madhav Chauhan
c5f9c93493 drm/i915/icl: Allocate DSI hosts and imlement host transfer 
Allocate DSI host structure for each DSI port available on gen11 and
register them with DSI fwk of DRM. Some of the DSI host operations are
also registered as part of this.

Retrieves DSI pkt (from DSI msg) to be sent over DSI link using DRM DSI
exported functions. A wrapper function is also added as "DSI host
transfer" for sending DSI data/cmd. Add DSI packet payload to command
payload queue using credit based mechanism for *long* packets.

v2 by Jani:
 - indentation
 - Use the new credit available helper
 - Use int for free_credits
 - Add intel_dsi local variable for better code flow
 - Use the new credit available helper
 - Use int for free_credits, i, and j

v3 by Jani:
 - Squash DSI host allocation and transfer patches together

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/af4f168ed8737d44687d8b6f21ecaa7e805eb695.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:05 +02:00
Madhav Chauhan
972d607c59 drm/i915/icl: Fill DSI ports info 
This patch fills backlight, CABC and general port
info for Gen11 DSI.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/48c9f867d61a60dc7c2ce744ac2325655652c55f.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:54:01 +02:00
Vandita Kulkarni
95f2f4dbb1 drm/i915/icl: Use the same pll functions for dsi 
The same pll manager functions can be used to enable dpll for
mipi. Hence enabling the IO power and esc clock as part of pre pll
enable call.

v2 by Jani:
- fix function parameter indent (Madhav)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/07db5b1ce59c00295fad8a8e81908d59d8d76915.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:53:58 +02:00
Madhav Chauhan
e275804873 drm/i915/icl: Allocate DSI encoder/connector 
This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired mode info to connector.

v2 by Jani:
 - Drop GEN11 prefix from encoder name
 - Drop extra parenthesis
 - Drop extra local variable
 - Squash encoder power domain here

v3 by Jani:
 - Squash connector and connector helper functions here
 - Move intel_dsi_vbt_init call here

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0197023b92ffa2d59064e30fd4ca22b6a4cff16c.1543500286.git.jani.nikula@intel.com
 2018-12-03 15:53:51 +02:00
Madhav Chauhan
70a057b7d4 drm/i915/icl: Calculate DPLL params for DSI 
This patch calculates various DPLL dividers and
parameters for DSI encoder and adjust AFE clock
for DSI. For DSI, 8x clock is AFE clock.

v2: Extend haswell_crtc_compute_clock() for Gen11 DSI

v3: Rebase

v4: use port clock instead of bitrate.

v5: Reabse and remove divide by 5

v6 by Jani:
- Fix indent (Madhav)
- Fix dpll state calc for EDP and DP MST

Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/525d41d0d893dcdc8874d2ce70afa226227ea3f4.1543500285.git.jani.nikula@intel.com
 2018-12-03 15:53:42 +02:00