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8018 Commits

Author SHA1 Message Date
Slava Abramov
f4557923b5 drm/amdgpu: fix typo in amdgpu_mn.c comments 
In doc comments for struct amdgpu_mn: destrution -> destruction

Signed-off-by: Slava Abramov <slava.abramov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:43 -05:00
Christian König
ad7f0b6334 drm/amdgpu: fix documentation of amdgpu_mn.c v2 
And wire it up as well.

v2: improve the wording, fix label mismatch

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:43 -05:00
Christian König
528e083d85 drm/amdgpu: rename rmn to amn in the MMU notifier code (v2) 
Just a copy&paste leftover from radeon.

v2: rebase (Alex)

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:42 -05:00
Harry Wentland
abea57d70e drm/amdgpu: Add BRACKET_LAYOUT_ENUMs to ObjectID.h 
DC has an upcoming change that requires these to read the board layout.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:42 -05:00
Junwei Zhang
59d61be222 drm/amdgpu: remove unused parameter for va update 
Don't need validation list any more

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: David Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:42 -05:00
David Panariti
04ad26bbc4 drm/amdgpu: Add plumbing for handling SQ EDC/ECC interrupts v2. 
SQ can generate interrupts and installs the ISR to
handle the SQ interrupts.

Add parsing SQ data in interrupt handler.

v2:
Remove CZ only limitation.
Rebase.

Signed-off-by: David Panariti <David.Panariti@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:41 -05:00
David Panariti
981658c67a drm/amdgpu: Add interrupt SQ source struct to amdgpu_gfx struct v2. 
SQ can generate interrupts on EDC/ECC errors and this struct controls
how the interrupt is handled.  The guts are filled in in the
gf_v<major>_<minor>.c files.

v2:
Rebase.

Signed-off-by: David Panariti <David.Panariti@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:41 -05:00
David Panariti
5a2f291343 drm/amdgpu: Added ISR for CP ECC/EDC interrupt v2. 
ISR will DRM_ERROR ECC error message.

v2:
Remove CZ only limitation.
Rebase.

Signed-off-by: David Panariti <David.Panariti@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:41 -05:00
Shirish S
8f4039fefd drm/amdgpu: change gfx8 ib test to use WB 
This patch is extends the usage of WB in
gfx8's ib test which was originally
implemented in the below upstream patch
"ed9324a drm/amdgpu: change gfx9 ib test to use WB"

For reference below are the reasons for switching
to WB:

1)Because when doing IB test we don't want to involve KIQ health
status affect, and since SCRATCH register access is go through
KIQ that way GFX IB test would failed due to KIQ fail.

2)acccessing SCRATCH register cost much more time than WB method
because SCRATCH register access runs through KIQ which at least could
begin after GPU world switch back to current Guest VF

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:40 -05:00
Emily Deng
11528640c7 drm/amdgpu: Correct the ndw of bo update mapping. 
For buffer object that has shadow buffer, need twice commands.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:40 -05:00
Boyuan Zhang
b7e6cd5702 drm/amdgpu: add AMDGPU_HW_IP_VCN_JPEG to queue mgr 
Add AMDGPU_HW_IP_VCN_JPEG to queue mgr

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:40 -05:00
Boyuan Zhang
4bafe44024 drm/amdgpu: add AMDGPU_HW_IP_VCN_JPEG to info query 
Add AMDGPU_HW_IP_VCN_JPEG to info query

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:39 -05:00
Boyuan Zhang
5b2329b618 drm/amdgpu: enable vcn jpeg ib test 
Enable vcn jpeg ib ring test in amdgpu_ib.c

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:38 -05:00
Boyuan Zhang
6173040f16 drm/amdgpu: add vcn jpeg ib test 
Add an ib test for vcn jpeg.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:38 -05:00
Boyuan Zhang
b1d3760645 drm/amdgpu: add vcn jpeg ring test 
Add a ring test for vcn jpeg.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:38 -05:00
Boyuan Zhang
0c5e4b3e1e drm/amdgpu: add vcn jpeg sw finish 
Add software finish for vcn jpeg ring.

v2: remove unnecessary scheduler entity.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:37 -05:00
Boyuan Zhang
b7fe681e35 drm/amdgpu: add patch to jpeg ring 
Add patch commands to jepg ring by calling set patch ring function.

v2: remove modifications on max_dw, buf_mask and ptr_mask, since we are
now using extra_dw for jpeg ring.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:37 -05:00
Boyuan Zhang
c8c1a1d2ef drm/amdgpu: define and add extra dword for jpeg ring 
Define extra dword for jpeg ring. Jpeg ring will allocate extra dword to store
the patch commands for fixing the known issue.

v2: dropping extra_dw for rings other than jpeg.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:37 -05:00
Boyuan Zhang
8a998052f2 drm/amdgpu: implement patch for fixing a known bug 
Implement a patch to maunally reset read pointer

v2: using ring assignment instead of amdgpu_ring_write. adding comments
for each steps in the patch function.
v3: fixing a typo bug.
v4: fixing a bug in v3.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:36 -05:00
Boyuan Zhang
d2314b48d6 drm/amdgpu: initialize vcn jpeg ring 
Add implementations for vcn jpeg ring initialization

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:36 -05:00
Boyuan Zhang
59dd2b883f drm/amdgpu: add vcn jpeg irq support 
Add vcn jpeg irq support.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:36 -05:00
Boyuan Zhang
e612bcc3ab drm/amdgpu: set jpeg ring functions 
Set all vcn jpeg ring function pointers.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:35 -05:00
Boyuan Zhang
221f36c460 drm/amdgpu: implement jpeg ring functions 
Implement all ring functions needed for jpeg ring

v2: remove unnecessary mem read function.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:35 -05:00
Boyuan Zhang
50613395ab drm/amdgpu: add more jpeg register offset headers 
Add more jpeg registers defines that are needed for jpeg ring functions

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:35 -05:00
Boyuan Zhang
d521093a5f drm/amdgpu: add jpeg packet defines to soc15d.h 
Add new packet for vcn jpeg, including condition checks, types and packet

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:34 -05:00
Boyuan Zhang
fa3087f768 drm/amdgpu: add vcn jpeg ring 
Add jpeg to amdgpu_vcn

v2: remove unnecessary scheduler entity

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:34 -05:00
Boyuan Zhang
8e0fce5a96 drm/amdgpu: define vcn jpeg ring 
Add AMDGPU_RING_TYPE_VCN_JPEG ring define

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:34 -05:00
Andrey Grodzovsky
48ad368a8a drm/amdgpu: move amdgpu_ctx_mgr_entity_fini to f_ops flush hook (V4) 
With this we can now terminate jobs enqueue into SW queue the moment
the task is being killed instead of waiting for last user of
drm file to release it.

Also stop checking for kref_read(&ctx->refcount) == 1 when
calling drm_sched_entity_do_release since other task
might still hold a reference to this entity but we don't
care since KILL means terminate job submission regardless
of what other tasks are doing.

v2:
Use returned remaining timeout as parameter for the next call.
Rebase.

v3:
Switch to working with jiffies.
Streamline remainder TO usage.
Rebase.

v4:
Rebase.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:33 -05:00
Michel Dänzer
2472e11b85 drm/amdgpu: Fix-ups for amdgpu_object.c documentation 
* Fix format of return value descriptions
* Document all parameters of amdgpu_bo_free_kernel
* Document amdgpu_bo_get_preferred_pin_domain

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:32 -05:00
Shirish S
8f4805a265 drm/amdgpu: avoid sleep while executing atombios table (V2) 
This patch replaces kzalloc's flag from GFP_KERNEL to
GFP_ATOMIC to avoid sleeping in atomic context.

Below is the stack trace:

BUG: sleeping function called from invalid context at mm/slab.h:***
in_atomic(): 1, irqs_disabled(): 0, pid: 1137, name: DrmThread
CPU: 1 PID: 1137 Comm: DrmThread Tainted: G        W       4.14.43 #10
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 __kmalloc+0x76/0x126
 amdgpu_atom_execute_table_locked+0xfc/0x285
 amdgpu_atom_execute_table+0x5d/0x72
 transmitter_control_v1_5+0xef/0x11a
 hwss_edp_backlight_control+0x132/0x151
 dce110_disable_stream+0x133/0x16e
 core_link_disable_stream+0x1c5/0x23b
 dce110_reset_hw_ctx_wrap+0xb4/0x1aa
 dce110_apply_ctx_to_hw+0x4e/0x6da
 ? generic_reg_get+0x1f/0x33
 dc_commit_state+0x33f/0x3d2
 amdgpu_dm_atomic_commit_tail+0x2cf/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 drm_atomic_helper_commit+0xdc/0xf9
 drm_atomic_helper_set_config+0x5c/0x76
 __drm_mode_set_config_internal+0x64/0x105
 drm_mode_setcrtc+0x474/0x56f
 ? drm_mode_getcrtc+0x155/0x155
 drm_ioctl_kernel+0x6c/0xa8
 drm_ioctl+0x267/0x353
 ? drm_mode_getcrtc+0x155/0x155
 amdgpu_drm_ioctl+0x4f/0x7f
 vfs_ioctl+0x21/0x2f
 do_vfs_ioctl+0x4c4/0x4e7
 ? security_file_ioctl+0x3b/0x4f
 SyS_ioctl+0x57/0x79
 do_syscall_64+0x64/0x72
 entry_SYSCALL_64_after_hwframe+0x3d/0xa2

V2: Added stack trace in commit message.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:31 -05:00
Michel Dänzer
baca30fabd drm/amdgpu: Add documentation for PRIME related code 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:31 -05:00
Alex Deucher
3120e2a390 drm/amdgpu/pp: switch the default dpm implementation for CI 
Switch hawaii and bonaire to use powerplay rather than the old
dpm implementation.  Powerplay supports more features and is
better maintained.  Ultimately, we can drop the older dpm
implementation like we did for other older asics.

Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:30 -05:00
Alex Deucher
d1a9146b3a drm/amdgpu/display: enable CONFIG_DRM_AMD_DC_DCN1_0 by default 
It's required for displays on Raven.  The DCN bandwidth calcs use
floating point, but DCN is APU only and it already depends on
X86.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:30 -05:00
Alex Deucher
5099114ba3 drm/amdgpu/display: drop DRM_AMD_DC_FBC kconfig option 
Just enable it always.  This was leftover from feature
bring up.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:29 -05:00
Samuel Li
6f4e8d6e59 drm/amdgpu: add kernel doc for amdgpu_object.c 
Document the amdgpu buffer object API.

v2: Add a DOC section and some more clarification.
v3: Add some clarification and fix a spelling.

Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:28 -05:00
Tony Cheng
0ce55b4676 drm/amd/display: dal 3.1.47 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:28 -05:00
Dmytro Laktyushkin
0dd6cfe15c drm/amd/display: add dentist frequency to resource pool 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:28 -05:00
Eric Bernstein
0b126112e9 drm/amd/display: DP YCbCr 4:2:0 support 
Update MSA MISC1 bit 6 programming to handle YCbCr 4:2:0
and BT2020 cases.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:27 -05:00
Reza Amini
8de94233f4 drm/amd/display: Prefix TIMING_STANDARD entries with DC_ 
Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:27 -05:00
Tony Cheng
e0d4234982 drm/amd/display: dal 3.1.46 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:27 -05:00
Yasir Al Shekerchi
a27f199677 drm/amd/display: Added documentation for some DC interface functions 
Signed-off-by: Yasir Al Shekerchi <YasirAl.Shekerchi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:26 -05:00
Vitaly Prosyak
43610a9be1 drm/amd/display: HLG support 
Low level calculation methods.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:26 -05:00
Anthony Koo
1a05873f21 drm/amd/display: Refactor audio programming 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:26 -05:00
Krunoslav Kovac
4ea209073d drm/amd/display: Dynamic HDR metadata mem buffer 
Basic framework:
- caps for reporting dynamic HDR metadata support
- allocation of frame buffer memory and storage

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:25 -05:00
Nikola Cornij
3c8e4316a0 drm/amd/display: Optimize DP_SINK_STATUS_ESI range read on HPD 
DP_SINK_STATUS_ESI range data is not continual, but rather than
getting it in two AUX reads, it's quicker to read more bytes in a
AUX read and then memcpy the required fields (it's only 8 more
bytes to read).

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:25 -05:00
Aric Cyr
bf58968647 drm/amd/display: Default log masks should include all connectivity events 
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:25 -05:00
Hersen Wu
cb1d7eacb5 drm/amd/display: Fix indentation in dcn10 resource constructor 
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:24 -05:00
Anthony Koo
8ca8090085 drm/amd/display: add DPCD read for Sink ieee OUI 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:24 -05:00
Eric Bernstein
0f6ca3bac4 drm/amd/display: Add function to get optc active size 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:24 -05:00
Hersen Wu
73770ca53f drm/amd/display: AUX will exit when HPD LOW detected 
This change shorten wait time when HPD LOW. With HPD LOW, without this
change, AUX routine delay is 450us. With this change, it is 42us.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:23 -05:00