Pull "ARMv7 VExpress fixes for v4.10" from Sudeep Holla:
A simple fix to extend GICv2 CPU interface registers from 4K to 8K
on VExpress TC1 and TC2 platforms in order to support split priority
drop and interrupt deactivation.
* tag 'vexpress-fixes-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress: Support GICC_DIR operations
Pull "i.MX fixes for 4.10" from Shawn Guo:
- A format fix for vf610-zii-dev-rev-b.dts, which has a very odd line
due to misses a newline.
- A fix to imx-weim bus error seen on board which doesn't actually use
the bus.
- A fix for imx6qdl-nitrogen6x board which has conflicting usage of
pad NANDF_CS2.
- A cleanup on i.MX1 machine to remove .map_io callback, which also
fixes a compiling error for NOMMU build.
- Fix AVIC base address in i.MX31 device tree source. The problem was
shadowed by the AVIC driver, which takes the correct base address
from a SoC specific header file.
* tag 'imx-fixes-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6: Disable "weim" node in the dtsi files
ARM: i.MX: remove map_io callback
ARM: dts: vf610-zii-dev-rev-b: Add missing newline
ARM: dts: imx6qdl-nitrogen6x: remove duplicate iomux entry
ARM: dts: imx31: fix AVIC base address
Pull "Qualcomm ARM DTS Fixes for v4.10-rc2" from Andy Gross:
* Add SCM clock for APQ8064 to fix boot failures
* tag 'qcom-arm-fixes-for-4.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
ARM: dts: qcom: apq8064: Add missing scm clock
Pull "omap fixes for v4.10-rc cycle" from Tony Lindgren:
Fist set of fixes for omaps for v4.10-rc cycle, mostly
to deal with various regressions noticed during the merge
window and to fix various device tree configurations for
boards. Also included is removal of mach-omap2/gpio.c that
is now dead code with device tree based booting that should
be OK for the early -rc cycle:
- A series of fixes to add empty chosen node to fix regressions
caused for bootloaders that don't create chosen node as the
decompressor needs the chosen node to merge command line and
ATAGs into it
- Fix missing logicpd-som-lv-37xx-devkit.dtb entry in Makefile
- Fix regression for am437x timers
- Fix wrong strcat for non-NULL terminated string
- A series of changes to fix tps65217 interrupts to not use
defines as we don't do that for interrupts
- Two patches to fix USB VBUS detection on am57xx-idk and force it
to peripheral mode until dwc3 role detection is working
- Add missing dra72-evm-tps65917 missing voltage supplies
accidentally left out of an earlier patch
- Fix n900 eMMC detection when booted on qemu
- Remove unwanted pr_err on failed memory allocation for
prm_common.c
- Remove legacy mach-omap2/gpio.c that now is dead code
since we boot mach-omap2 in device tree only mode
- Fix am572x-idk pcie1 by adding the missing gpio reset pin
* tag 'omap-for-v4.10/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (23 commits)
ARM: dts: am572x-idk: Add gpios property to control PCIE_RESETn
ARM: OMAP2+: PRM: Delete an error message for a failed memory allocation
ARM: dts: n900: Mark eMMC slot with no-sdio and no-sd flags
ARM: dts: dra72-evm-tps65917: Add voltage supplies to usb_phy, mmc, dss
ARM: dts: am57xx-idk: Put USB2 port in peripheral mode
ARM: dts: am57xx-idk: Support VBUS detection on USB2 port
dt-bindings: input: Specify the interrupt number of TPS65217 power button
dt-bindings: power/supply: Update TPS65217 properties
dt-bindings: mfd: Remove TPS65217 interrupts
ARM: dts: am335x: Fix the interrupt name of TPS65217
ARM: omap2+: fixing wrong strcat for Non-NULL terminated string
ARM: omap2+: am437x: rollback to use omap3_gptimer_timer_init()
ARM: dts: omap3: Add DTS for Logic PD SOM-LV 37xx Dev Kit
ARM: dts: dra7: Add an empty chosen node to top level DTSI
ARM: dts: dm816x: Add an empty chosen node to top level DTSI
ARM: dts: dm814x: Add an empty chosen node to top level DTSI
ARM: dts: am4372: Add an empty chosen node to top level DTSI
ARM: dts: am33xx: Add an empty chosen node to top level DTSI
ARM: dts: omap5: Add an empty chosen node to top level DTSI
ARM: dts: omap4: Add an empty chosen node to top level DTSI
...
Samsung mach/soc update for v4.10:
1. Minor cleanup in smp_operations.
2. Another step in switching s3c24xx to new DMA API.
3. Drop fixed requirement for HZ=200 on Samsung platforms.
* tag 'samsung-soc-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: Drop fixed 200 Hz timer requirement from Samsung platforms
ARM: S3C24XX: Add DMA slave maps for remaining s3c24xx SoCs
ARM: EXYNOS: Remove smp_init_cpus hook from platsmp.c
Qualcomm ARM64 Fixes for v4.10-rc1
* Fix instability in MSM8996 due to incorrect carveouts
* tag 'qcom-fixes-for-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: msm8996: Add required memory carveouts
There are two versions of the clearfog - a base and a pro model. The
base model has an additional PHY on eth1, replacing the DSA switch on
the pro model. MPP assignments are slightly different. The base model
also omits the second PCIe, and footprint for a PIC microcontroller.
In order to cater for these differences, move all the existing clearfog
support to a dtsi file before starting to modify it, to make the
following changes more clear.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Move the SDHCI pinctrl node to the microsom file - the microsom can have
optional eMMC support which uses these same pinctrl settings, so it is
sensible to have these here.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The optional SPI flash is fitted to the microsom, not the clearfog
board, so it should be specified in the microsom DTS include file.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The SPI flash #size-cells is specified in the binding documentation to
have value 1, but we were setting it to zero. This wasn't causing any
problem as we do not list any partitions, but it's worth specifying
correctly if we're going to specify it at all.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add OX820 dt-bindings includes files for clocks and resets, replace
resets numbers by human readable defines.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add OX810SE dt-bindings includes files for clocks and resets, replace
resets numbers by human readable defines.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
MARVELL_PHY - support for the Marvell PHY that is on most of the devkits
EEPROM_AT24 - support for I2C EEPROMs on the devkits
GPIO_ALTERA - support for Altera's GPIO driver
NAND - support for the Denali NAND controller along with MTD subsystem
SPI_DESIGNWARE - support for SPI that is on SoCFPGA
SPI_DW_MMIO - support for the memory-mapped io interface for the DW SPI core
OF_CONFIGFS - SoCFPGA makes use of DT overlays using configfs, enable it
GPIO_ALTERA_A10SR - support for the newly added Altera HWMON driver
LEDS - support for the GPIO LEDs on the SoCFPGA devkits
RTC - support for the DS1307 RTC
JFFS2_FS - support for the JFFS2 filesystem
NFS_V4 - supports for v4 NFS
FUNCTION_TRACER - supports debug function tracing
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
The BCM958712DxXMC board is a smaller form factor typically used as
controller boards for switches. This smaller board has less devices
pinned out, so only a few need be populated in the device tree.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Nitro firmware is loaded into memory by the bootloader at a specific
location. Set this memory range aside to prevent the kernel from using
it.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This enables the PAXC based PCIe root complex on NS2 SVK. The PAXC based
root complex is connected to internally emulated PCIe endpoints
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
PAXB and PAXC PCIe interfaces on NS2 have been using the iProc event
queue to handle MSI. With the gicv2m support ready, we should now switch
to gicv2m for MSI handling
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Pull parisc updates from Helge Deller:
- limit usage of processor-internal cr16 clocksource to UP systems only
- segfault info lines in syslog were too long, split those up
- drop own TIF_RESTORE_SIGMASK flag and switch to generic code
* 'parisc-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
parisc: Add line-break when printing segfault info
parisc: Drop TIF_RESTORE_SIGMASK and switch to generic code
parisc: Mark cr16 clocksource unstable on SMP systems
Al Viro noticed that we were using two different methods to filter out
flags from KBUILD_CFLAGS.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reported-by: Al Viro <viro@zeniv.linux.org.uk>
The L1 data cache in I6400 CPUs is indexed by physical address bits if
an entry for the address is present in the DTLB early enough in the
pipelined execution of a memory access instruction. If an entry is not
present then it's indexed by virtual address bits, but hardware will
check in a later pipeline stage when a DTLB entry has been created
whether the virtual address bits used match the physical address bits,
and if not will transparently restart the memory access instruction.
This means that although it isn't always physically indexed, it appears
so to software & we can treat the I6400 L1 data cache as being
physically indexed in order to avoid considering aliasing.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14016/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The netlogic platform can be built for either MIPS32 or MIPS64, and when
built for MIPS32 (as by nlm_xlr_defconfig) the use of the dla
pseudo-instruction leads to warnings such as the following from recent
versions of the GNU assembler:
arch/mips/netlogic/common/smpboot.S: Assembler messages:
arch/mips/netlogic/common/smpboot.S:62: Warning: dla used to load 32-bit register; recommend using la instead
arch/mips/netlogic/common/smpboot.S:63: Warning: dla used to load 32-bit register; recommend using la instead
Avoid these warnings by using the PTR_LA macro to make use of the
appropriate la or dla pseudo-instruction for the build.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 66d29985fa ("MIPS: Netlogic: Merge some of XLR/XLP wakup code")
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14185/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Now that EXPORT_SYMBOL can be used from assembly source, move the
EXPORT_SYMBOL invocations for the copy_page & clear_page functions to be
alongside their definitions.
With this change there are no longer any symbols exported from
mips_ksyms.c so remove the file.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14515/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
When building a kernel targeting a microMIPS ISA, recent GNU linkers
will fail the link if they cannot determine that the target of a branch
or jump is microMIPS code, with errors such as the following:
mips-img-linux-gnu-ld: arch/mips/built-in.o: .text+0x542c:
Unsupported jump between ISA modes; consider recompiling with
interlinking enabled.
mips-img-linux-gnu-ld: final link failed: Bad value
or:
./arch/mips/include/asm/uaccess.h:1017: warning: JALX to a
non-word-aligned address
Placing anything other than an instruction at the start of a function
written in assembly appears to trigger such errors. In order to prepare
for allowing us to follow function prologue macros with an EXPORT_SYMBOL
invocation, end the prologue macros (LEAD, NESTED & FEXPORT) with a
.insn directive. This ensures that the start of the function is marked
as code, which always makes sense for functions & safely prevents us
from hitting the link errors described above.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14508/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
When generating TLB exception handling code we write to memory reserved
at the handle_tlbl, handle_tlbm & handle_tlbs symbols. Up until now the
ISA bit has always been clear simply because the assembly code reserving
the space for those functions places no instructions in them. In
preparation for marking all LEAF functions as containing code,
explicitly clear the ISA bit when calculating the addresses at which to
write TLB exception handling code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14507/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Arch-specific implementation of arch_uprobe_copy_ixol is expected to
override the weak implementation in generic code.
As currently both implementations are marked as weak, it is up to the
linker to chose one. Remove the __weak attribute from MIPS code to make
sure the correct version is used.
Fixes: 40e084a506 ("MIPS: Add uprobes support.")
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14660/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
