Stephen Boyd
7fa50aa559
Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next
...
* clk-hisi-usb:
clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC
* clk-silent-bulk:
clk: bulk: silently error out on EPROBE_DEFER
* clk-mtk-hdmi:
clk: mediatek: correct the clocks for MT2701 HDMI PHY module
* clk-mtk-mali:
clk: mediatek: add g3dsys support for MT2701 and MT7623
dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
dt-bindings: clock: mediatek: add g3dsys bindings
* clk-imx6ul-ccosr:
clk: imx: Add new clo01 and clo2 controlled by CCOSR
2018-06-04 12:27:40 -07:00
Sean Wang
aa9bb8d19d
dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
...
Just add binding for a required clock referenced by Mali-450 on MT7623
or MT2701 SoC.
Cc: devicetree@vger.kernel.org
Signed-off-by: Sean Wang <sean.wang@mediatek.com >
Reviewed-by: Rob Herring <robh@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2018-05-15 15:21:43 -07:00
Ryder Lee
bf61099a21
clk: mediatek: correct the clocks for MT2701 HDMI PHY module
...
The hdmitx_dig_cts clock signal is not a child of clk26m,
and the actual output of the PLL block is derived from
the tvdpll via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Fixes: e986211827chunhui.dai@mediatek.com >
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2018-05-15 15:17:49 -07:00
Sean Wang
55a5fcafe3
dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
...
Just add binding for a fixed-factor clock axisel_d4, which would be
referenced by PWM devices on MT7623 or MT2701 SoC.
Cc: stable@vger.kernel.org
Fixes: 1de9b21633sean.wang@mediatek.com >
Reviewed-by: Rob Herring <robh@kernel.org >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: devicetree@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2018-03-19 13:25:09 -07:00
Sean Wang
43ed50ee5a
clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
...
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org >
Signed-off-by: Sean Wang <sean.wang@mediatek.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-06-19 19:02:44 -07:00
Shunli Wang
1de9b21633
clk: mediatek: Add dt-bindings for MT2701 clocks
...
Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com >
Signed-off-by: James Liao <jamesjj.liao@mediatek.com >
Signed-off-by: Erin Lo <erin.lo@mediatek.com >
Tested-by: John Crispin <blogic@openwrt.org >
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2016-08-19 12:18:41 -07:00
