Commit Graph

3592 Commits

Author SHA1 Message Date
Magnus Damm
4d76ad7d9d arm64: dts: renesas: r8a77965: Attach the SYS-DMAC to the IPMMU
For R-Car M3-N hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to
IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car M3-W.
This follows the R-Car Gen3 Rev.1.00 (April 2018) datasheet.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13 09:47:14 +02:00
Biju Das
90493b09df arm64: dts: renesas: Initial r8a774a1 SoC device tree
Basic support for the RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13 09:47:12 +02:00
Kieran Bingham
e3da41a6c2 arm64: dts: renesas: salvator-common: adv748x: Override secondary addresses
Ensure that the ADV748x device addresses do not conflict, and group them
together (visually in i2cdetect)

Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13 09:47:11 +02:00
Sergei Shtylyov
3182aa4e0b arm64: dts: renesas: r8a77980: add CSI2/VIN support
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13 09:47:10 +02:00
Wolfram Sang
3a0832d093 arm64: dts: renesas: salvator-xs: enable SATA
Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
off for that to work.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13 09:47:10 +02:00
Takeshi Kihara
346f02270a arm64: dts: renesas: r8a77965: Add SATA controller node
This patch adds SATA controller node for the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[wsa: rebased to upstream base]
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13 09:47:03 +02:00
Neil Armstrong
2250e0f57a arm64: dts: meson-axg-s400: Add chosen and memory nodes
Add missing chosen and memory nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:57:27 -07:00
Neil Armstrong
eaf8f57c0b arm64: dts: meson-axg: use the proper compatible for ethmac
Use the correct compatible for the AXG ethernet mac node.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:55:29 -07:00
Jerome Brunet
d85163c7ee arm64: dts: meson-axg: s400: add pdm to the sound card
Enable the PDM input device on the S400 and it to the sound card

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:51:28 -07:00
Jerome Brunet
63d1e75742 arm64: dts: meson-axg: s400: add dmic codec
There are 7 digital mics on the MIC daughter board attached
to the s400 board, so add the digital microphone codec to
its DTS

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:51:28 -07:00
Jerome Brunet
c362e4e005 arm64: dts: meson-axg: add pdm
Add the PDM device of the axg audio subsystem

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:51:28 -07:00
Maxime Jourdan
f172604342 arm64: dts: meson-gx: add dmcbus and canvas nodes.
DMC is a small memory region with various registers,
including the ones needed for the canvas module.

Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:41:38 -07:00
Jerome Brunet
b7eb0e26cc arm64: dts: meson: libretech: update board model
There is actually several different libretech board with the CC suffix
so the model name is not appropriate here. Update to something more
specific

Reported-by: Da Xue <da@lessconfused.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:41:37 -07:00
Christian Hewitt
4cbef415c9 arm64: dts: meson-gx: increase default shared CMA pool size
Devices using the new V4L2 mem2mem vdec require a larger CMA pool. As
nearly all GX* devices are video/media focused and will use it, set a
larger (256MB) default value.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:41:28 -07:00
Jerome Brunet
8c0cf40f06 arm64: dts: meson-axg: sort nodes consistently
Sort DT nodes by address when possible, by node node name otherwise.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-12 21:14:33 -07:00
Icenowy Zheng
b2ad66f546 arm64: dts: allwinner: h6: add system controller device tree node
As we have already binding for the H6 system controller, add its node
to the device tree.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[fixed compatible string]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-12 22:49:43 +08:00
Sergei Shtylyov
18281dec2b arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
device  trees,  according to  the alphanumeric node sorting rule...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11 15:49:48 +02:00
Sergei Shtylyov
f14bfabc54 arm64: dts: renesas: r8a77980: move IPMMU nodes
The IPMMU nodes should follow the GEther node, not the CAN-FD node,
according to the <unit-address> part of the startng IPMMU-DS1 node.
While moving the nodes, also do sort them by label alphanumerically...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11 15:49:47 +02:00
Yoshihiro Shimoda
180485566d arm64: dts: renesas: r8a77990: Enable PWM for Ebisu board
This patch adds PWM device nodes and enables PWM3 and PWM5 for
R-Car E3 Ebisu board. These devices are used for backlight control.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11 15:49:46 +02:00
Sergei Shtylyov
0dba24a8e1 arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77980 SoC's device tree.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11 15:49:45 +02:00
Suzuki K Poulose
79daf2a408 arm64: dts: juno: Enable coresight tmc scatter gather in ETR
We do not enable scatter-gather mode in the TMC-ETR by default
to prevent malfunctioning of systems where the ETR may not be
properly connected to the memory subsystem to allow for simultaneous
READ/WRITE transactions when used in SG mode. Instead we whitelist
the platforms where we know that it is safe to use the mode.

All revisions of Juno have a proper ETR connection and hence
white list them.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pierlisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2018-09-11 11:41:28 +01:00
Vicente Bergas
78f26da3ff arm64: dts: rockchip: Add type-c port supply on rk3399-sapphire board
Add the gpio-controlled regulator and add the supply to the otg-port of phy0.

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-10 19:16:26 +02:00
Katsuhiro Suzuki
ef05bcb60c arm64: dts: rockchip: fix vcc_host1_5v pin assign on rk3328-rock64
This patch fixes pin assign of vcc_host1_5v. This regulator is
controlled by USB20_HOST_DRV signal.

ROCK64 schematic says that GPIO0_A2 pin is used as USB20_HOST_DRV.
GPIO0_D3 pin is for SPDIF_TX_M0.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-10 15:06:42 +02:00
Shohei Maruyama
a5002c41c3 arm64: dts: rockchip: add WiFi module support for Firefly-RK3399
This commit adds WiFi module support for the Firefly-RK3399.

Signed-off-by: Shohei Maruyama <cheat.sc.linux@outlook.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-10 14:50:16 +02:00
Vicente Bergas
707fa9e37f arm64: dts: rockchip: remove dvs2 pinctrl from pmic on rk3399-sapphire
On the board DVS2 is disabled and not connected, see schematic, page 16.

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-10 14:05:55 +02:00
Vicente Bergas
bcdb578a5f arm64: dts: rockchip: Fix VCC5V0_HOST_EN on rk3399-sapphire
The pin is GPIO4-D1 not GPIO1-D1, see schematic, page 15 for reference.

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-10 14:03:52 +02:00
Vicente Bergas
07736689dc arm64: dts: rockchip: re-order vcc_sys on rk3399-sapphire
Fix alphabetical order.

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-10 14:02:28 +02:00
Suzuki K Poulose
41af6cbfa1 arm64: dts: juno: Update entries to match latest coresight bindings
Switch to updated coresight bindings for Juno platforms.

Cc: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[sudeep.holla: minor modifications to patch title]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2018-09-10 10:27:41 +01:00
Jagan Teki
0b1ea6f357 arm64: dts: allwinner: h6: Add OrangePi One Plus initial support
OrangePi One Plus is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- 1Gbps GMAC via RTL8211
- USB 2.0 Host, OTG
- HDMI port
- 5V/2A DC power supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-04 23:06:07 +08:00
Kurt Kanzenbach
470104ae72 arm64: dts: ls208xa: add second duart
The NXP LS208xA SoCs have two dual uarts. Thus, add the second one.

Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03 12:25:37 +08:00
Prabhakar Kushwaha
5b39601cd3 arm64: dts: fsl: remove big-endian field from IFC controller
As per IFC binding, Absence of "little-endian" field causes registers
access in big-endian mode.
So no need to set explicit big-endian field IFC node for LS1043A and
LS1046A.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03 12:25:37 +08:00
Prabhakar Kushwaha
03444ad87b arm64: dts: Add big-endian in nor node for ls104xa
NOR and IFC controller connectivity is big-endian.
So add big-endian field in nor device tree node allowing
IFC controller to read/write data from/to the flash correctly.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03 12:25:37 +08:00
Chen-Yu Tsai
1b6ff1cb7e arm64: dts: allwinner: a64: Rename r_i2c_pins_a label to r_i2c_pl89_pins
The pinmux name and label for a specific function should denote which
pingroup it is on, or if there is only one option for the function, have
not enumerating prefix/suffix at all.

The "r_i2c_pins_a" label is renamed to "r_i2c_pl89_pins" to fit our
current style. The node name "i2c" is also changed to "r-i2c-pl89-pins"
to match. The reason for the peculiar name is that the other option for
muxing R_I2C is on the PL0/PL1 pins, so the name has to mention the pin
numbers in addition to the pingroup.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-03 10:59:52 +08:00
Chen-Yu Tsai
d91ebb95b9 arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins
The pinmux name and label for a specific function should denote which
pingroup it is on, or if there is only one option for the function, have
not enumerating prefix/suffix at all.

The "uart0_pins_a" label is renamed to "uart0_pb_pins" to fit our
current style. The node name "uart0" is also changed to "uart0-pb-pins"
to match.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-03 10:59:37 +08:00
Chen-Yu Tsai
fa59dd2ef7 arm64: dts: allwinner: a64: Split out data strobe pin from mmc2 pinmux
The eMMC 5.0 standard introduced the data strobe (DS) pin. This pin is
not used for pre-5.0 data modes, nor is it found on pre-5.0 eMMC chips.
On the A64, this pin is muxed with spi0's MISO pin. If the DS pin is
included in the mmc2 pinmux by default, this wil prevent the usage
of both mmc2 and spi0 together.

Instead, split out the DS pin to a separate pinmux that only gets used
by boards that actually have it wired up. Currently supported ones
include the Bananapi M64 and Pine64 Pinebook. These are fixed up.

Fixes: a3e8f49262 ("arm64: allwinner: a64: Add MMC pinctrl nodes")
Fixes: b8bcf0e1b2 ("arm64: allwinner: add BananaPi-M64 support")
Fixes: df35fbcfa3 ("arm64: dts: allwinner: add support for Pinebook")
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-03 10:59:16 +08:00
Stefan Wahren
a7eb26392b arm64: dts: broadcom: Add reference to Compute Module IO Board V3
This adds a reference to the dts of the Compute Module IO Board V3 in arm,
so we don't need to maintain the content in arm64.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
2018-08-31 07:01:34 +02:00
Alan Tull
c8da1d15b8 arm64: dts: stratix10: i2c clock running out of spec
DesignWare I2C controller was observed running at 105.93kHz rather
than the specified 100kHz.  Adjust device tree settings to bring it
within spec (a slightly conservative 98 MHz).

Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-08-30 08:38:26 -05:00
Jerome Brunet
6f59dc1afb arm64: dts: meson-axg: s400: add sound card
Add the sound card of the s400. With it the following interface
should be working:
 * Lineout
 * Daugther card speaker 1 (same output as lineout)
 * Linein
 * SPDIF output

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-08-29 08:38:21 -07:00
Jerome Brunet
a0ef1c1cc8 arm64: dts: meson-axg: s400: enable audio devices
Enable the audio devices on the s400.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-08-29 08:38:21 -07:00
Jerome Brunet
f2b8f6a933 arm64: dts: meson-axg: add audio fifos
Add TODDR and FRDDR audio fifos of the AXG SoC.
These fifos are the capture and playback memory interfaces of audio
subsystem of the AXG.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-08-29 08:38:20 -07:00
Sandy Huang
967c146491 arm64: dts: rockchip: add missing vop properties for px30
Add display ports for display-subsystem and add reset property
for vop node. If missing these properties, drm driver can't
probe sucessfully.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-08-29 14:54:08 +02:00
Tony Xie
f888da1662 arm64: dts: rockchip: Add idle-states to device tree for rk3399
Add idle-states for cpu and cluster sleep states.

Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-08-29 14:23:06 +02:00
Kunihiko Hayashi
925c5c32f3 arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3
Add nodes of SPI controller for UniPhier SoCs.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28 23:17:55 +09:00
Masahiro Yamada
bae120f8ac arm64: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.

For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28 23:14:55 +09:00
Laurent Pinchart
58e8ed2ee9 arm64: dts: renesas: Convert to new LVDS DT bindings
The internal LVDS encoder now has DT bindings separate from the DU. Port
the r8a7795 and r8a7796 device trees over to the new model.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27 15:06:16 +02:00
Magnus Damm
dc7a6bab2b arm64: dts: renesas: r8a77995: Attach the SYS-DMAC to the IPMMU
Hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to IPMMU-DS0 and IPMMU-DS1
following the R-Car Gen3 Rev.1.00 (April 2018) datasheet.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27 15:06:16 +02:00
Magnus Damm
e18a31a7ad arm64: dts: renesas: Include R-Car product name in DTSI files
Browsing the DTS for all the R-Car SoCs with similar part numbers
makes my head hurt, so to improve the user friendliness of the
DTS code base include R-Car product name in each DTSI file.

Product names are derived from
Documentation/devicetree/bindings/arm/shmobile.txt

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27 15:06:16 +02:00
Sergei Shtylyov
bcee502ceb arm64: dts: renesas: r8a77980: add RWDT support
Describe RWDT in the R8A77980 SoC device tree.

Enable RWDT on the Condor and V3H Starter Kit boards.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27 15:06:15 +02:00
Aapo Vienamo
207f60babb arm64: dts: tegra186: Enable HS400
Enable HS400 signaling on Tegra186 SDMMC4 controller.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27 12:27:37 +02:00
Aapo Vienamo
d5d6b468a0 arm64: dts: tegra210: Enable HS400
Enable HS400 signaling on Tegra210 SDMMC4 controller.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27 12:27:37 +02:00