Add omap-usb3 and omap-usb2 data node in OMAP5 device tree file.
The information for the node added here is available @
Documentation/devicetree/bindings/usb/usb-phy.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add ocp2scp data node in omap5 device tree file.
The information for the node added here can be found @
Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap control usb data in OMAP5 device tree file.
This will have the register address of registers to
power on the USB2 PHY and USB3 PHY.
The information for the node added here is available in
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add usb otg data node in omap4/omap3 device tree file. Also update
the node with board specific setting in omapx-<board>.dts file.
The dt data specifies among others the interface type (ULPI or UTMI),
mode which is mostly OTG, power that specifies the amount of power
this can supply when in host mode.
The information about usb otg node is available @
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap-usb2 data node in omap4 device tree file. Since omap-usb2
is connected to ocp2scp, omap-usb2 dt data is added as a child node
of ocp2scp. The information about this data node is availabe @
Documentation/devicetree/bindings/usb/usb-phy.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap control usb data in omap4 device tree file. This will have the
register address of registers to power on the PHY and to write to
mailbox. The information about this data node is available @
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Currently the OMAP General-Purpose Memory Controller (GPMC) device
node maps 16 MB of address space for its hardware registers.
This is because the OMAP Technical Reference Manual says that the
GPMC module register address space size is 16 MB. But in practice
the maximum address offset used by a GPMC register is 0x02d0.
So, there is no need to map such a big address space for GPMC regs.
This change was suggested by Jon Hunter [1].
[1]: https://patchwork.kernel.org/patch/2057111/
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap4 panda results in the following error
[ 0.444427] omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 0.445770] omap_i2c 48070000.i2c: bus 0 rev0.11 at 400 kHz
[ 0.473937] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 0.474670] omap_i2c 48072000.i2c: bus 1 rev0.11 at 400 kHz
[ 0.474822] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 0.476379] omap_i2c 48060000.i2c: bus 2 rev0.11 at 100 kHz
[ 0.477294] omap_i2c 48350000.i2c: did not get pins for i2c error: -19
[ 0.477996] omap_i2c 48350000.i2c: bus 3 rev0.11 at 400 kHz
[ 0.483398] Switching to clocksource 32k_counter
This happens because omap4 panda dts file is not adapted to use i2c through
pinctrl framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap4460 panda with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Luciano Coelho <coelho@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap 5430evm results in the following error
omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
[ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
[ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19
[ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
This happens because omap5 dts file is not adapted to use i2c through pinctrl
framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap5430 evm with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap 4430sdp results in the following error
omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
[ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
[ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19
[ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
This happens because omap4 dts file is not adapted to use i2c through pinctrl
framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap4430 sdp with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
We have proper driver stack to handle the pmu_stat LED which is connected
PWMB of twl4030.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add a new address space/memory resource to d_can device tree node. D_CAN
RAM initialization is achieved through RAMINIT register which is part of
AM33XX control module address space. D_CAN RAM init or de-init should be
done by writing instance corresponding value to control module register.
Till we have a separate control module driver to write to control module,
d_can driver will handle the register writes to control module by itself.
So a new address space to represent this control module register is added
to d_can driver.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add d_can instances to aliases node to get the D_CAN instance number
from the driver. To initialize D_CAN message RAM, corresponding instance
number is required.
To initialize instance 0 message RAM then 0x1 should be written and for
instance 1 message RAM, 0x2 should be written to control module register.
With device-tree framework ip instance number is "-1" by default for all
instances. To get device id/instance number then modules should be added
to DT "aliases" node. of_alias_get_id() gives the device id number based
on number of alias nodes present in "aliases node".
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
ISEE IGEP COM Module is an TI OMAP3 SoC computer on module.
This patch adds an initial device tree support to boot an
IGEP COM Module from the MMC/SD.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
[b-cousson@ti.com: Update the Makefile for 3.8-rc2]
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
ISEE IGEPv2 is an TI OMAP3 SoC based embedded board.
This patch adds an initial device tree support to boot
an IGEPv2 from the MMC/SD.
Currently is working everything that is supported by DT
on OMAP3 SoCs (MMC/SD, GPIO LEDs, EEPROM, TWL4030 audio).
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
[benoit.cousson@linaro.org: Update the Makefile for 3.8-rc2]
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Rename I2C and GPIO nodes according to AM33XX TRM. According to
AM33XX TRM device instances are starting from "0" like i2c0, i2c1
and i2c3.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
[panto@antoniou-consulting.com: initial patch by pantelis's]
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
In the early days, the A10 and A13 shared quite some code. Nowadays it
shares less and less code, the A31 diverging even more, so it doesn't
make much sense to continue to maintain this structure, just use one
DTSI for every SoC, and that's it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
From Maxime Ripard <maxime.ripard@free-electrons.com>:
ARM: sunxi: dt additions for 3.10, take 2
- Rename the clock compatible introduced in the first pull request for 3.10
- Complete the UART support for A13 and A10
- Adds clock gates support
* tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux:
arm: sunxi: Add clock to pinctrl node
arm: sunxi: use the right clock phandles for UARTs
arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
ARM: sunxi: cubieboard: Add UART muxing
ARM: sunxi: hackberry: Add UART muxing
ARM: sunxi: dt: Add A10 UARTs to the dtsi.
ARM: sunxi: dt: Add uart3 dt node
ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi
ARM: sunxi: Rename uart nodes to serial
ARM: sunxi: dt: Use clocks property instead of clock-frequency for the UARTs
arm: sunxi: rename clock compatible strings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: bcm2835: device tree updates
This branch adds two devices to the BCM2835 SoC device tree: the SPI
controller and the HW random number generator.
The SPI controller isn't actually instantiated in the Raspberry Pi
device tree, since there are no on-board SPI devices; it's up to the
end-user to modify their own device-tree to describe whatever they
have attached.
* tag 'bcm2835-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: add Broadcom BCM2835 RNG to the device tree
ARM: bcm2835: add SPI device to DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Tony Lindgren <tony@atomide.com>:
Clean-up for omap2+ timers from Jon Hunter <jon-hunter@ti.com>:
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on 7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and 960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of 7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
* tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: Fix sparse warning in system timers
ARM: OMAP2+: Store ID of system timers in timer structure
ARM: OMAP3: Update clocksource timer selection
ARM: OMAP2+: Simplify system timers definitions
ARM: OMAP2+: Simplify system timer clock definitions
ARM: OMAP2+: Remove hard-coded test on timer ID
ARM: OMAP2+: Display correct system timer name
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Tony Lindgren <tony@atomide.com>:
EHCI platform data related changes for v3.10 merge window.
These are needed for the USB PHY support, and are based on
commit 1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
* tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: omap3-beagle: Add USB Host support
ARM: dts: OMAP3: Add HS USB Host IP nodes
ARM: dts: OMAP4: Add HS USB Host IP nodes
ARM: OMAP: zoom: Adapt to ehci-omap changes
ARM: OMAP3: overo: Adapt to ehci-omap changes
ARM: OMAP3: omap3touchbook: Adapt to ehci-omap changes
ARM: OMAP3: omap3stalker: Adapt to ehci-omap changes
ARM: OMAP3: omap3pandora: Adapt to ehci-omap changes
ARM: OMAP3: omap3evm: Adapt to ehci-omap changes
ARM: OMAP3: igep0020: Adapt to ehci-omap changes
ARM: OMAP: devkit8000: Adapt to ehci-omap changes
ARM: OMAP3: cm-t3517: Adapt to ehci-omap changes
ARM: OMAP3: cm-t35: Adapt to ehci-omap changes
ARM: OMAP: AM3517evm: Adapt to ehci-omap changes
ARM: OMAP: AM3517crane: Adapt to ehci-omap changes
ARM: OMAP3: 3630SDP: Adapt to ehci-omap changes
ARM: OMAP3: 3430SDP: Adapt to ehci-omap changes
ARM: OMAP3: Beagle: Adapt to ehci-omap changes
ARM: OMAP2+: omap4panda: Adapt to ehci-omap changes
ARM: OMAP2+: omap-usb-host: Add usbhs_init_phys()
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds a arm-pmu node to bind device tree for exynos4210.
The exynos4210 and 4212 have two cpus which includes a pmu. In contrast, the
exynos4412 has 4 cpus and pmus. We need to define two more pmus for this type
board. However, supporting arm-pmu for the exynos4412 will handle it later
because there is no dts support for 4412 based board.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
From Michal Simek <michal.simek@xilinx.com>:
This branch is based on zynq/clksrc/cleanup parts because
there are some dependencies on moving timer to generic location.
I could based it on standard Linux tagged version but you will get
several conflicts you will have to resolve.
If you are OK to resolving these problems, please let me know
I will create another branch with core-smp changes which are not based
on zynq/clksrc/cleanup branch.
* 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Add hotplug support
arm: zynq: Add smp support
arm: zynq: Add smp_twd timer
arm: zynq: Get rid of xilinx function prefix
arm: zynq: Add support for system reset
arm: zynq: Move slcr initialization to separate file
arm: zynq: Load scu baseaddress at run time
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add cpufreq controller device node for Exynos5440 SoC for passing
parameters like controller base address, interrupt and cpufreq
table. This node is added outside cpu0 as this driver is now a platform
driver and a new device structure is needed.
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Exynos5440 common clock driver has changed the clock ID's for
some of the clocks. Fix the gmac clock entries in Exynos5440 dtsi
file accordingly.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Updated the bootargs to boot the system with rootfs in /dev/sda2
instead of ramdisk.
Signed-off-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
PMU in exynos5440 generates one interrupt per core and needs to be
passed from DT to GIC to register it.
Signed-off-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds node for GMAC for exynos5440 SoC supported by GMAC
driver.
Signed-off-by: Byungho An <bh74.an@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5440 pin-controller generates eight interrupts to support
gpio interrupts. List those interrupt numbers in the pin-controller
node.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds device tree node for the SYSREG registers block
found in Samsung S5P/Exynos SoC series. The SYSREG module
generates control signals for the ARM CPU and various IP blocks
and buses. SYSREG block registers are exposed through APB bus
interface. A sysreg device tree node is to be associated with
mfd syscon driver and all SYSREG clients should use regmap
interface it provides. It allows to eliminate any possible races
and conflicts should different drivers attempt to concurrently
access same register.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
