Jeremy Compostella
e2724e9d96
x86/tsc: Add missing Cherrytrail frequency to the table
...
Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4
means that the CPU reference clock runs at 80MHz. Add this missing
frequency to the table.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com >
Link: http://lkml.kernel.org/r/87y47gty89.fsf@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de >
2016-05-12 14:27:14 +02:00
Yazen Ghannam
14cddfd530
x86/mce: Update AMD mcheck init to use cpu_has() facilities
...
Use cpu_has() facilities to find available RAS features rather than
directly reading CPUID 0x80000007_EBX.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
[ Use the struct cpuinfo_x86 ptr instead. ]
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462971509-3856-6-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-12 09:08:22 +02:00
Yazen Ghannam
71faad4306
x86/cpu: Add detection of AMD RAS Capabilities
...
Add a new CPUID leaf to hold the contents of CPUID 0x80000007_EBX (RasCap).
Define bits that are currently in use:
Bit 0: McaOverflowRecov
Bit 1: SUCCOR
Bit 3: ScalableMca
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
[ Shorten comment. ]
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462971509-3856-5-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-12 09:08:22 +02:00
Borislav Petkov
e128b4f483
x86/mce/AMD: Save an indentation level in prepare_threshold_block()
...
Do the !SMCA work first and then save us an indentation level for the
SMCA code.
No functionality change.
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: Yazen Ghannam <Yazen.Ghannam@amd.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462971509-3856-4-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-12 09:08:21 +02:00
Yazen Ghannam
32544f0603
x86/mce/AMD: Disable LogDeferredInMcaStat for SMCA systems
...
Disable Deferred Error logging in MCA_{STATUS,ADDR} additionally for
SMCA systems as this information will retrieved from MCA_DE{STAT,ADDR}
on those systems.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
[ Simplify, drop SMCA_MCAX_EN_OFF define too. ]
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462971509-3856-3-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-12 09:08:20 +02:00
Yazen Ghannam
3410200958
x86/mce/AMD: Log Deferred Errors using SMCA MCA_DE{STAT,ADDR} registers
...
Scalable MCA provides new registers for all banks for logging deferred
errors: MCA_DESTAT and MCA_DEADDR. Deferred errors are always logged to
these registers.
Update the AMD deferred error handler to use these registers, if
available.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
[ Sanity-check __log_error() args, massage a bit. ]
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462971509-3856-2-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-12 09:08:19 +02:00
Ingo Molnar
d2950158d0
Merge branch 'perf/urgent' into perf/core, to pick up fixes
...
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-11 16:56:38 +02:00
Borislav Petkov
f0133acc7d
x86/cpu: Correct comments and messages in P4 erratum 037 handling code
...
Remove the linebreak in the conditional and s/errata/erratum/ as the
singular is "erratum".
No functionality change.
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/1462733920-7224-1-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-10 10:05:03 +02:00
Thomas Gleixner
8d415ee225
x86/topology: Set x86_max_cores to 1 for CONFIG_SMP=n
...
Josef reported that the uncore driver trips over with CONFIG_SMP=n because
x86_max_cores is 16 instead of 12.
The reason is, that for SMP=n the extended topology detection is a NOOP and
the cache leaf is used to determine the number of cores. That's wrong in two
aspects:
1) The cache leaf enumerates the maximum addressable number of cores in the
package, which is obviously not correct
2) UP has no business with topology bits at all.
Make intel_num_cpu_cores() return 1 for CONFIG_SMP=n
Reported-by: Josef Bacik <jbacik@fb.com >
Signed-off-by: Thomas Gleixner <tglx@linutronix.de >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: kernel-team <Kernel-team@fb.com >
Cc: Kan Liang <kan.liang@intel.com >
Link: http://lkml.kernel.org/r/761b4a2a-0332-7954-f030-c6639f949612@fb.com
2016-05-10 09:28:31 +02:00
Chris Wilson
01e5d3b42e
x86: Silence 32bit compiler warning in intel_graphics_stolen()
...
arch/x86/kernel/early-quirks.c: In function ‘intel_graphics_stolen’:
arch/x86/kernel/early-quirks.c:539:9: warning: format ‘%llx’ expects
argument of type ‘long long unsigned int’, but argument 2 has type ‘phys_addr_t’ [-Wformat=]
"0x%llx-0x%llx\n", base, base + size - 1);
^
arch/x86/kernel/early-quirks.c:539:9: warning: format ‘%llx’ expects
argument of type ‘long long unsigned int’, but argument 3 has type ‘phys_addr_t’ [-Wformat=]
v2: Use %pa for addresses
Fixes: ee0629cfd3chris@chris-wilson.co.uk >
Cc: Daniel Vetter <daniel.vetter@ffwll.ch >
Cc: Mika Kuoppala <mika.kuoppala@intel.com >
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com >
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Ingo Molnar <mingo@redhat.com >
Cc: "H. Peter Anvin" <hpa@zytor.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com > #v1
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1462811982-1567-1-git-send-email-chris@chris-wilson.co.uk
2016-05-10 09:17:42 +03:00
Thomas Gleixner
56402d63ee
x86/topology: Handle CPUID bogosity gracefully
...
Joseph reported that a XEN guest dies with a division by 0 in the package
topology setup code. This happens if cpu_info.x86_max_cores is zero.
Handle that case and emit a warning. This does not fix the underlying XEN bug,
but makes the code more robust.
Reported-and-tested-by: Joseph Salisbury <joseph.salisbury@canonical.com >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com >
Cc: David Vrabel <david.vrabel@citrix.com >
Link: http://lkml.kernel.org/r/alpine.DEB.2.11.1605062046270.3540@nanos
Signed-off-by: Thomas Gleixner <tglx@linutronix.de >
2016-05-07 10:06:55 +02:00
Ingo Molnar
35dc9ec107
Merge branch 'linus' into efi/core, to pick up fixes
...
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-07 07:00:07 +02:00
Linus Torvalds
3f86ba5d0c
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
...
Pull x86 fixes from Ingo Molnar:
"This contains two fixes: a boot fix for older SGI/UV systems, and an
APIC calibration fix"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO
x86/platform/UV: Bring back the call to map_low_mmrs in uv_system_init
2016-05-06 12:59:27 -07:00
Chen Yu
886123fb3a
x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO
...
Currently we read the tsc radio: ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f;
Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the SDM
(35.5), the ratio bits are bit 8-15.
Ignoring the upper bits can result in an incorrect tsc ratio, which causes the
TSC calibration and the Local APIC timer frequency to be incorrect.
Fix this problem by masking 0xff instead.
[ tglx: Massaged changelog ]
Fixes: 7da7c15613yu.c.chen@intel.com >
Cc: "Rafael J. Wysocki" <rafael@kernel.org >
Cc: stable@vger.kernel.org
Cc: Bin Gao <bin.gao@intel.com >
Cc: Len Brown <lenb@kernel.org >
Link: http://lkml.kernel.org/r/1462505619-5516-1-git-send-email-yu.c.chen@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de >
2016-05-06 11:50:50 +02:00
Wang YanQing
c10fcb14c7
x86/sysfb_efi: Fix valid BAR address range check
...
The code for checking whether a BAR address range is valid will break
out of the loop when a start address of 0x0 is encountered.
This behaviour is wrong since by breaking out of the loop we may miss
the BAR that describes the EFI frame buffer in a later iteration.
Because of this bug I can't use video=efifb: boot parameter to get
efifb on my new ThinkPad E550 for my old linux system hard disk with
3.10 kernel. In 3.10, efifb is the only choice due to DRM/I915 not
supporting the GPU.
This patch also add a trivial optimization to break out after we find
the frame buffer address range without testing later BARs.
Signed-off-by: Wang YanQing <udknight@gmail.com >
[ Rewrote changelog. ]
Signed-off-by: Matt Fleming <matt@codeblueprint.co.uk >
Reviewed-by: Peter Jones <pjones@redhat.com >
Cc: <stable@vger.kernel.org >
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org >
Cc: David Herrmann <dh.herrmann@gmail.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com >
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/1462454061-21561-2-git-send-email-matt@codeblueprint.co.uk
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-05 16:01:00 +02:00
Ingo Molnar
1a618c2cfe
Merge branch 'perf/urgent' into perf/core, to pick up fixes
...
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-05 10:12:37 +02:00
Ingo Molnar
3cd0b53553
Merge branch 'x86/urgent' into x86/platform, to resolve conflict
...
Conflicts:
arch/x86/kernel/apic/x2apic_uv_x.c
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-05 09:56:10 +02:00
Alex Thorlton
08914f436b
x86/platform/UV: Bring back the call to map_low_mmrs in uv_system_init
...
A while back the following commit:
d394f2d9d8d2f7cbe7b2d394f2d9d8athorlton@sgi.com >
Cc: Matt Fleming <matt@codeblueprint.co.uk >
Cc: Adam Buchbinder <adam.buchbinder@gmail.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Borislav Petkov <bp@suse.de >
Cc: Russ Anderson <rja@sgi.com >
Cc: Dimitri Sivanich <sivanich@sgi.com >
Link: http://lkml.kernel.org/r/1462401592-120735-1-git-send-email-athorlton@sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-05 09:55:02 +02:00
Ingo Molnar
f3391a160b
Merge tag 'v4.6-rc6' into x86/cpu, to refresh the tree
...
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-05 08:41:36 +02:00
Sinan Kaya
9e5ed6d1fb
ACPI,PCI,IRQ: remove SCI penalize function
...
Removing the SCI penalize function as the penalty is now calculated on the
fly.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org >
Acked-by: Bjorn Helgaas <bhelgaas@google.com >
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com >
2016-05-05 01:10:32 +02:00
Dimitri Sivanich
f68376fc9e
x86/platform/UV: Fix incorrect nodes and pnodes for cpuless and memoryless nodes
...
This patch fixes the problem of incorrect nodes and pnodes being returned
when referring to nodes that either have no cpus (AKA "headless") or no
memory.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Dimitri Sivanich <sivanich@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215406.192644884@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:51 +02:00
Mike Travis
c85375cd19
x86/platform/UV: Update physical address conversions for UV4
...
This patch builds support for the new conversions of physical addresses
to and from sockets, pnodes and nodes in UV4. It is designed to be as
efficient as possible as lookups are done inside an interrupt context
in some cases. It will be further optimized when physical hardware is
available to measure execution time.
Tested-by: Dimitri Sivanich <sivanich@sgi.com >
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215405.841051741@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:50 +02:00
Mike Travis
6e27b91cf4
x86/platform/UV: Build GAM reference tables
...
An aspect of the UV4 system architecture changes involve changing the
way sockets, nodes, and pnodes are translated between one another.
Decode the information from the BIOS provided EFI system table to build
the needed conversion tables.
Tested-by: Dimitri Sivanich <sivanich@sgi.com >
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215405.673495324@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:50 +02:00
Mike Travis
1de329c10d
x86/platform/UV: Support UV4 socket address changes
...
With the UV4 system architecture addressing changes, BIOS now provides
this information via an EFI system table. This is the initial decoding
of that system table. It also collects the sizing information for
later allocation of dynamic conversion tables.
Tested-by: Dimitri Sivanich <sivanich@sgi.com >
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215405.503022681@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:50 +02:00
Mike Travis
405422d88c
x86/platform/UV: Add UV4 addressing discovery function
...
UV4 requires early system wide addressing values. This involves the use
of the CPUID instruction to obtain these values. The current function
(detect_extended_topology()) in the kernel has been copied and streamlined,
with the limitation that only CPU's used by UV architectures are supported.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215405.155660884@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:49 +02:00
Mike Travis
906f3b20da
x86/platform/UV: Fold blade info into per node hub info structs
...
Migrate references from the blade info structs to the per node hub info
structs. This phases out the allocation of the list of per blade info
structs on node 0, in favor of a per node hub info struct allocated on
the node's local memory.
There are also some minor cosemetic changes in the comments and whitespace
to clean things up a bit.
Tested-by: Dimitri Sivanich <sivanich@sgi.com >
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215404.987204515@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:49 +02:00
Mike Travis
3edcf2ff7a
x86/platform/UV: Allocate common per node hub info structs on local node
...
Allocate and setup per node hub info structs. CPU 0/Node 0 hub info
is statically allocated to be accessible early in system startup. The
remaining hub info structs are allocated on the node's local memory,
and shared among the CPU's on that node. This leaves the small amount
of info unique to each CPU in the per CPU info struct.
Memory is saved by combining the common per node info fields to common
node local structs. In addtion, since the info is read only only after
setup, it should stay in the L3 cache of the local processor socket.
This should therefore improve the cache hit rate when a group of cpus
on a node are all interrupted for a common task.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Reviewed-by: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215404.813051625@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:49 +02:00
Mike Travis
5627a8251f
x86/platform/UV: Move blade local processor ID to the per cpu info struct
...
Move references to blade local processor ID to the new per cpu info
structs. Create an access function that makes this move, and other
potential moves opaque to callers of this function. Define a flag
that indicates to callers in external GPL modules that this function
replaces any local definition. This allows calling source code to be
built for both pre-UV4 kernels as well as post-UV4 kernels.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215404.644173122@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:49 +02:00
Mike Travis
d38bb135d8
x86/platform/UV: Move scir info to the per cpu info struct
...
Change the references to the SCIR fields to the new per cpu info structs.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215404.452538234@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:49 +02:00
Mike Travis
0045ddd23f
x86/platform/UV: Create per cpu info structs to replace per hub info structs
...
The major portion of the hub info is common to all cpus on that hub.
This is step one of moving the per cpu hub info to a per node hub info
struct. This patch creates the small per cpu info struct that will
contain only information specific to each CPU.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215404.282265563@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:48 +02:00
Mike Travis
a2f28e6950
x86/platform/UV: Update MMIOH setup function to work for both UV3 and UV4
...
Since UV3 and UV4 MMIOH regions are setup the same, we can use a common
function to setup both.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215404.100504077@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:48 +02:00
Mike Travis
b608f87fe8
x86/platform/UV: Clean up redunduncies after merge of UV4 MMR definitions
...
Clean up any redundancies caused by new UV4 MMR definitions superseding
any previously definitions local to functions.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Reviewed-by: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215403.934728974@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:48 +02:00
Mike Travis
c443c03dd0
x86/platform/UV: Prep for UV4 MMR updates
...
Cleanup patch to rearrange code and modify some defines so the next
patch, the new UV4 MMR definitions can be merged cleanly.
* Clean up the M/N related address constants (M is # of address bits per
blade, N is the # of blade selection bits per SSI/partition).
* Fix the lookup of the alias overlay addresses and NMI definitions to
allow for flexibility in newer UV architecture types.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215403.401604203@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:47 +02:00
Mike Travis
7563421b13
x86/platform/UV: Add UV MMR Illegal Access Function
...
This new function is generated by the UV MMR generation script to
identify MMR registers and fields that are not defined for a specific
UV architecture. With this switch, the immediate panic can be replaced
with a message and a bad return value allowing either hardware or the
emulator to diagnose the problem. It allows functions common to some
UV arches to use common defines that might not be fully defined for all
arches, as long as they do not reference them on the unsupported arches.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215403.231926687@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:47 +02:00
Mike Travis
a0ec83f316
x86/platform/UV: Add UV4 Specific Defines
...
Add UV4 specific defines to determine if current system type is a
UV4 system.
Tested-by: John Estabrook <estabrook@sgi.com >
Tested-by: Gary Kroening <gfk@sgi.com >
Tested-by: Nathan Zimmer <nzimmer@sgi.com >
Signed-off-by: Mike Travis <travis@sgi.com >
Reviewed-by: Dimitri Sivanich <sivanich@sgi.com >
Cc: Andrew Banman <abanman@sgi.com >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Len Brown <len.brown@intel.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Russ Anderson <rja@sgi.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/20160429215403.072323684@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-04 08:48:47 +02:00
Stas Sergeev
0b4521e8cf
signals/sigaltstack, x86/signals: Unify the x86 sigaltstack check with other architectures
...
Currently x86's get_sigframe() checks for "current->sas_ss_size"
to determine whether there is a need to switch to sigaltstack.
The common practice used by all other arches is to check for
sas_ss_flags(sp) == 0
This patch makes the code consistent with other architectures.
The slight complexity of the patch is added by the optimization on
!sigstack check that was requested by Andy Lutomirski: sas_ss_flags(sp)==0
already implies that we are not on a sigstack, so the code is shuffled
to avoid the duplicate checking.
This patch should have no user-visible impact.
Signed-off-by: Stas Sergeev <stsp@list.ru >
Cc: Al Viro <viro@zeniv.linux.org.uk >
Cc: Andrew Morton <akpm@linux-foundation.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Borislav Petkov <bp@suse.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Oleg Nesterov <oleg@redhat.com >
Cc: Pavel Emelyanov <xemul@parallels.com >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Richard Weinberger <richard@nod.at >
Cc: Shuah Khan <shuahkh@osg.samsung.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: linux-api@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/1460665206-13646-2-git-send-email-stsp@list.ru
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:37:58 +02:00
Yazen Ghannam
fead35c689
x86/mce: Detect local MCEs properly
...
Check the MCG_STATUS_LMCES bit on Intel to verify that current MCE is
local. It is always local on AMD.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
[ Massaged it a bit. Reflowed comments. Shut up -Wmaybe-uninitialized. ]
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462019637-16474-8-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:24:17 +02:00
Tony Luck
5541c93cdf
x86/mce: Look in genpool instead of mcelog for pending error records
...
A couple of issues here:
1) MCE_LOG_LEN is only 32 - so we may have more pending records than will
fit in the buffer on high core count CPUs.
2) During a panic we may have a lot of duplicate records because multiple
logical CPUs may have seen and logged the same error because some
banks are shared.
Switch to using the genpool to look for the pending records. Squeeze out
duplicated records.
Signed-off-by: Tony Luck <tony.luck@intel.com >
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Ashok Raj <ashok.raj@intel.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462019637-16474-7-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:24:16 +02:00
Yazen Ghannam
d9d73fcc87
x86/mce: Detect and use SMCA-specific msr_ops
...
Replace all calls to MCx_IA32_{CTL,ADDR,MISC,STATUS} with the
appropriate msr_ops.
Use SMCA-specific msr_ops when on an SMCA-enabled processor.
Carved out from a patch by Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com >.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462019637-16474-6-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:24:16 +02:00
Yazen Ghannam
a9750a31ef
x86/mce: Define vendor-specific MSR accessors
...
Scalable MCA processors have a whole new range of MSR addresses to
obtain bank related info such as CTL, MISC, ADDR, STATUS. Therefore, we
need a way to abstract the MSR addresses per vendor.
Carved out from a patch by Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com >.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com >
Cc: Ashok Raj <ashok.raj@intel.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462019637-16474-5-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:24:16 +02:00
Aravind Gopalakrishnan
bb91f8c017
x86/mce: Carve out writes to MCx_STATUS and MCx_CTL
...
We need to do this after __mcheck_cpu_init_vendor() as for
ScalableMCA processors, there are going to be new MSR write handlers
if the feature is detected using CPUID bit (which happens in
__mcheck_cpu_init_vendor()).
No functional change is introduced here.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com >
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1462019637-16474-4-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:24:16 +02:00
Aravind Gopalakrishnan
6bda529ec4
x86/mce: Grade uncorrected errors for SMCA-enabled systems
...
For upcoming processors with Scalable MCA feature, we need to check the
"succor" CPUID bit and the TCC bit in the MCx_STATUS register in order
to grade an MCE's severity.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com >
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
[ Simplified code flow, shortened comments. ]
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1459886686-13977-3-git-send-email-Yazen.Ghannam@amd.com
Link: http://lkml.kernel.org/r/1462019637-16474-3-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:24:15 +02:00
Aravind Gopalakrishnan
10001d91aa
x86/mce: Log MCEs after a warm rest on AMD, Fam17h and later
...
For Fam17h, we want to report errors that persist across reboots. Error
persistence is dependent on HW and no BIOS currently fiddles with values
here. So allow reporting of errors upon boot until something goes wrong.
Logging is disabled on older families because BIOS didn't clear the MCA
banks after a cold reset.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com >
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com >
Signed-off-by: Borislav Petkov <bp@suse.de >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Tony Luck <tony.luck@intel.com >
Cc: linux-edac <linux-edac@vger.kernel.org >
Link: http://lkml.kernel.org/r/1459886686-13977-2-git-send-email-Yazen.Ghannam@amd.com
Link: http://lkml.kernel.org/r/1462019637-16474-2-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:24:15 +02:00
Ingo Molnar
b33f39e9d1
Merge tag 'v4.6-rc6' into ras/core, to refresh the tree
...
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-05-03 08:23:58 +02:00
Andy Lutomirski
c9867f863e
x86/tls: Synchronize segment registers in set_thread_area()
...
The current behavior of set_thread_area() when it modifies a segment that is
currently loaded is a bit confused.
If CS [1] or SS is modified, the change will take effect on return
to userspace because CS and SS are fundamentally always reloaded on
return to userspace.
Similarly, on 32-bit kernels, if DS, ES, FS, or (depending on
configuration) GS refers to a modified segment, the change will take
effect immediately on return to user mode because the entry code
reloads these registers.
If set_thread_area() modifies DS, ES [2], FS, or GS on 64-bit kernels or
GS on 32-bit lazy-GS [3] kernels, however, the segment registers
will be left alone until something (most likely a context switch)
causes them to be reloaded. This means that behavior visible to
user space is inconsistent.
If set_thread_area() is implicitly called via CLONE_SETTLS, then all
segment registers will be reloaded before the thread starts because
CLONE_SETTLS happens before the initial context switch into the
newly created thread.
Empirically, glibc requires the immediate reload on CLONE_SETTLS --
32-bit glibc on my system does *not* manually reload GS when
creating a new thread.
Before enabling FSGSBASE, we need to figure out what the behavior
will be, as FSGSBASE requires that we reconsider our behavior when,
e.g., GS and GSBASE are out of sync in user mode. Given that we
must preserve the existing behavior of CLONE_SETTLS, it makes sense
to me that we simply extend similar behavior to all invocations
of set_thread_area().
This patch explicitly updates any segment register referring to a
segment that is targetted by set_thread_area(). If set_thread_area()
deletes the segment, then the segment register will be nulled out.
[1] This can't actually happen since 0e58af4e1dluto@kernel.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/27d119b0d396e9b82009e40dff8333a249038225.1461698311.git.luto@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-04-29 11:56:42 +02:00
Andy Lutomirski
296f781a4b
x86/asm/64: Rename thread_struct's fs and gs to fsbase and gsbase
...
Unlike ds and es, these are base addresses, not selectors. Rename
them so their meaning is more obvious.
On x86_32, the field is still called fs. Fixing that could make sense
as a future cleanup.
Signed-off-by: Andy Lutomirski <luto@kernel.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/69a18a51c4cba0ce29a241e570fc618ad721d908.1461698311.git.luto@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-04-29 11:56:42 +02:00
Andy Lutomirski
731e33e39a
x86/arch_prctl/64: Remove FSBASE/GSBASE < 4G optimization
...
As far as I know, the optimization doesn't work on any modern distro
because modern distros use high addresses for ASLR. Remove it.
The ptrace code was either wrong or very strange, but the behavior
with this patch should be essentially identical to the behavior
without this patch unless user code goes out of its way to mislead
ptrace.
On newer CPUs, once the FSGSBASE instructions are enabled, we won't
want to use the optimized variant anyway.
This isn't actually much of a performance regression, it has no effect
on normal dynamically linked programs, and it's a considerably
simplification. It also removes some nasty special cases from code
that is already way too full of special cases for comfort.
Signed-off-by: Andy Lutomirski <luto@kernel.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/dd1599b08866961dba9d2458faa6bbd7fba471d7.1461698311.git.luto@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-04-29 11:56:41 +02:00
Andy Lutomirski
45e876f794
x86/segments/64: When loadsegment(fs, ...) fails, clear the base
...
On AMD CPUs, a failed loadsegment currently may not clear the FS
base. Fix it.
While we're at it, prevent loadsegment(gs, xyz) from even compiling
on 64-bit kernels. It shouldn't be used.
Signed-off-by: Andy Lutomirski <luto@kernel.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/a084c1b93b7b1408b58d3fd0b5d6e47da8e7d7cf.1461698311.git.luto@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-04-29 11:56:41 +02:00
Andy Lutomirski
35de5b0692
x86/asm: Stop depending on ptrace.h in alternative.h
...
alternative.h pulls in ptrace.h, which means that alternatives can't
be used in anything referenced from ptrace.h, which is a mess.
Break the dependency by pulling text patching helpers into their own
header.
Signed-off-by: Andy Lutomirski <luto@kernel.org >
Cc: Andy Lutomirski <luto@amacapital.net >
Cc: Borislav Petkov <bp@alien8.de >
Cc: Brian Gerst <brgerst@gmail.com >
Cc: Denys Vlasenko <dvlasenk@redhat.com >
Cc: H. Peter Anvin <hpa@zytor.com >
Cc: Linus Torvalds <torvalds@linux-foundation.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Link: http://lkml.kernel.org/r/99b93b13f2c9eb671f5c98bba4c2cbdc061293a2.1461698311.git.luto@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-04-29 11:56:40 +02:00
Ingo Molnar
ffc5fce9a9
Merge branch 'x86/urgent' into x86/asm, to refresh the tree
...
Signed-off-by: Ingo Molnar <mingo@kernel.org >
2016-04-29 11:55:04 +02:00
