It is not recommended to place the regulator nodes inside 'simple-bus',
so adjust them accordingly.
The motivation for rearranging this is to make it easier to add new
regulator nodes in the future.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The FEC driver ignores the GPIO polarity from 'phy-reset-gpios' and
considers that the Ethernet PHY is active low, unless the
property 'phy-reset-active-high' is present.
Fix the device tree description by explicitly passing the
'GPIO_ACTIVE_LOW' flag to the 'phy-reset-gpios' property.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The AR100 clock within the R_CCU (PRCM) has the PLL_PERIPH0 as one of
its parents.
This adds the reference in the device tree describing this relationship.
This patch uses a raw number for the clock index to ease merging by
avoiding cross tree dependencies.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.
The PRCM also has controls for various power domains. These are not
supported yet, neither in software nor in the device tree binding.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Exynos5250 and Exynos542x SoCs have the same CEC hardware module as
Exynos4 SoC series, so enable support for it using the same compatible
string.
Tested on Odroid XU3 (Exynos5422) and Google Snow (Exynos5250) boards.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Rockchip's rk3229 evaluation board has one usb otg controller
and three usb host controllers. Each usb controller connect
with one usb2 phy port through UTMI+ interface. And the three
usb host interfaces use the same GPIO VBUS drive. Let's enable
them to support usb on rk3229 evb board.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds usb otg/host controllers and phys nodes on rk322x.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This augments the Moxa Art and Aspeed device trees to:
- Explicitly name the clock "PCLK" as the Faraday FTTMR010
names it.
- List the Moxa timer as compatible with the Faradat FTTMR010
vanilla version.
- Add a comment that the Aspeed driver is a Faraday
FTTMR010 derivative.
- Pass all IRQs to the timer from Aspeed: they are all there
so they should be in the device tree, we only use the
first one anyways.
Tested-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This is a first set of Gemini DTS patches for the v4.13 cycle.
This adds the reset and clock lines to the Gemini core DTS SoC.
These bindings have been ACKed by the DT maintainer Rob.
The reset driver is going to be merged by the reset maintainer.
The clock driver is going to be merged by the clock maintainers.
Each of these have their macro defines coming with them, split
off as separate patches.
A post-rc1 patch will be sumbitted for switching the numerical
values to the defined macros in line with the ARM SoC DT header
merge strategy.
* tag 'gemini-v4.13-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: Add clocks to the Gemini SoC
ARM: dts: Add the Gemini reset controller
dt-bindings: Augment Gemini for clocks, resets
Signed-off-by: Olof Johansson <olof@lixom.net>
Renesas ARM Based SoC DT Updates for v4.13
* Switch to panel-lvds bindings for Mitsubishi panels
* Clean up PFC node names
* Enable UHS-I SDR-50 and SDR-104 on r8a7793/Gose
* Add GyroADC clock and device for r8a7791 SoC
* Add USB clocks to device tree for r7s72100 SoC
* tag 'renesas-dt-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: renesas: Switch to panel-lvds bindings for Mitsubishi panels
ARM: dts: gose: Enable UHS-I SDR-50 and SDR-104
ARM: dts: r8a7793: set maximum frequency for SDHI clocks
ARM: dts: r8a7791: Add GyroADC clock and device node
ARM: dts: r7s72100: add usb clocks to device tree
ARM: dts: sh73a0: update PFC node name to pin-controller
ARM: dts: r8a7793: update PFC node name to pin-controller
ARM: dts: r8a7791: update PFC node name to pin-controller
ARM: dts: r8a7790: update PFC node name to pin-controller
ARM: dts: r8a7779: update PFC node name to pin-controller
ARM: dts: r8a7778: update PFC node name to pin-controller
ARM: dts: r8a7740: update PFC node name to pin-controller
ARM: dts: r8a73a4: update PFC node name to pin-controller
ARM: dts: emev2: update PFC node name to pin-controller
ARM: dts: r7s72100: add USB bit definitions
ARM: dts: r7s72100: add Renesas RZ/A1 pinctrl header
ARM: dts: r8a7791: add GyroADC clock
Signed-off-by: Olof Johansson <olof@lixom.net>
Most of DT files in ARM use #include "..." to make pre-processor
include DT in the same directory, but this is one of the exceptional
files that use #include <...> for that.
Fix it to remove -I$(srctree)/arch/$(SRCARCH)/boot/dts path from
dtc_cpp_flags.
ARM: dts: versatile: use #include "..." to include DT in the same directory
Most of DT files in ARM use #include "..." to make pre-processor
include DT in the same directory, but we have 3 exceptional files
that use #include <...> for that.
They must be fixed to remove -I$(srctree)/arch/$(SRCARCH)/boot/dts
path from dtc_cpp_flags.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The only adc button connected to adc input is recovery button.
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Right now mach-imx6ul registers a fixup for the ksz8081 phy. The same
register values can be set through the micrel phy driver by using dts
properties.
This seems preferable and allows cleanly fixing suspend/resume.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
NanoPi M1 Plus is designed and developed by FriendlyElec
for professionals, enterprise users, makers and hobbyists
using the Allwinner H3 SOC.
NanoPi M1 Plus key features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 1GB DDR3 RAM
- 8GB eMMC
- microSD slot
- 10/100/1000M Ethernet
- Serial Debug Port
- 5V 2A DC power-supply
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the needed clock nodes for the CLKOUT2 to be usable by boards.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use the new EBI/NAND bindings to declare NAND chips and remove old NAND
nodes along the way.
Note that we keep using old bindings in at91rm9200.dtsi because this
SoC is not supported by the EBI driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
According to the binding documentation and the source code the atmel-gpio
controller takes IRQ_TYPE_* as its flags values, not GPIO_ACTIVE_*.
This patch uses the right variable type which yields the same result
when compiled. Note that this might be wrong and actually
IRQ_TYPE_LEVEL_LOW is intended by the dt author.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The gpio node has 144 gpios. Each gpio is capable of generating
an interrupt. Hence add interrupt-controller property to the gpio
node. With this in place one can use interrupts property in device
tree to request for the gpio interrupts.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds CPPI 4.1 DMA controller to USB OTG controller.
Changes since v2:
- Fixed the the property reg-names (had glue register defined)
- Removed few useless property
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add node for SPI NOR flash on orange-pi-zero board. Disable this node
by default and leave it to users to enable it if their board has
SPI NOR flash chip populated.
SPI NOR flash was optional in the first production batch in Dec 2016.
In later batches flash chip was pre-populated. However there should
be quite a few boards around which do not have flash chip.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The USB PHY can use either a GPIO pin or the PMIC's USB power supply
to sense VBUS. Since both options are available on the Cubietruck,
add the missing property for the USB power supply to the USB PHY node.
The device tree provides all usable options. Ultimately, which method
is used is up to the driver implementation.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ACIN pins of the AXP221 PMIC on the A31 Hummingbird are tied to the
DC jack on the board through a 12V to 5V buck converter.
Enable the ACIN power supply.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ACIN pins of the AXP209 PMIC on the Cubieboard are tied to the
DC jack on the board.
Enable the ACIN power supply.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ACIN pins of the AXP209 PMIC on the Bananapi M1 Plus are tied to the
"power input" micro USB connector next to the SATA connector on the board.
Enable the ACIN power supply.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ACIN pins of the AXP209 PMIC on the Cubieboard 2 are tied to the
DC jack on the board.
Enable the ACIN power supply.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
We want to keep node references in alphabetical order, except for
instances where node must be #included first.
Move the usb_otg node reference so that all references to non-AXP209
device nodes are in alphabetical order.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Two of the Ethernet switches on this board have EEPROMs connected.
Add the eeprom-length property to the device tree, making it possible
to access the EEPROM using ethtool -e.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch extends the L2 cache controller node for the Amlogic Meson8
and Meson8b SoCs with some missing parameters. These are taken from the
Amlogic GPL kernel source.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
[apply the change to Meson8 and Meson8b and updated description]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Currently only meson6.dtsi and meson8.dtsi inherit the generic
meson.dtsi. However, since the Meson8b platform is basically a slightly
updated version of Meson8 we can safely inherit meson.dtsi. An indicator
for this are the nodes which are identical in meson.dtsi and
meson8b.dtsi (L2, gic, timer, uart_AO, uart_A, uart_B, uart_C).
Additionally this makes the following devices available on Meson8b which
were not avaialble before (however, since all affected drivers support
Meson6, Meson8 and the whole GX series there's no reason to assume that
they are not working):
- i2c_a and i2c_B
- the IR receiver
- SPFIC (SPI flash controller)
- the dwmac ethernet controller
Differences between Meson8 and Meson8b seem to be:
- ARM Cortex-A5 core instead of Cortex-A9 on Meson8
- dwmac on Meson8b supports RGMII
- small pinctrl updates
Inheriting meson.dtsi makes it easier to maintain by removing duplicate
definitions.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The Amlogic Meson SoCs have most of the internal peripherals organized
in busses. Use them to make the dts easier to read and to avoid
duplicated register (bus) offset definitions.
The bus information is taken from the vendor kernel:
#define IO_CBUS_PHY_BASE 0xc1100000 ///2M
#define IO_AOBUS_PHY_BASE 0xc8100000 ///1M
There are more internal busses (such as the abp bus which seems to
contain audio, HDMI and Mali registers), but since we don't have
drivers for them yet these are not added (yet).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[khilman: minor whitespace fix]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Looks like nobody bothered to configure USB host for 37xx-evm
when we converted things to device tree, so let's add it. This
is similar to beagleboard configuration with few extra quirks
to configure the port. And as with beagleboard, OHCI won't work
because there is no USB LS/FS PHY. A HS USB hub is needed to use
devices like keyboard and mice.
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As long as the kernel cmdline has "earlycon" in it, this allows
seeing debug messages earlier and does not require DEBUG_LL to
be enabled.
Acked-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As long as the kernel cmdline has "earlycon" in it, this allows
seeing debug messages earlier and does not require DEBUG_LL to
be enabled.
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds the serial slave device for the WL1835 Bluetooth interface.
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable the System Mailboxes 5 and 6 and the corresponding
child sub-mailbox (IPC 3.x) nodes for the AM571x IDK board.
This is needed to enable communication with the respective
remote processors IPU1, IPU2, and DSP1 from the MPU.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable the System Mailboxes 5 and 6 and the corresponding
child sub-mailbox (IPC 3.x) nodes for the AM572x IDK board.
This is needed to enable communication with the respective
remote processors IPU1, IPU2, DSP1 and DSP2 from the MPU.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With two separate &gpmc nodes the second ranges property overwrites the
first. So put nand and ethernet in a single node and merge the ranges.
While at it also fix the ethernet suffix.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We don't need to bitbang these pins anymore, instead we muxed these
pins as SPI, after this change, done in commit 6c69f726, we introduced
the following error:
pinctrl-single 44e10800.pinmux: pin PIN85 already requested \
by 44e10800.pinmux; cannot claim for 48030000.spi
pinctrl-single 44e10800.pinmux: pin-85 (48030000.spi) status -22
Fixes: 6c69f726 ("ARM: dts: am335x-sl50: Enable SPI0 interface and Flash Memory")
Cc: <stable@vger.kernel.org> # 4.11
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The second version of the hardware moved the card detect pin from gpio0_6
to gpio1_9, as we won't support the first hardware version fix the pinmux
configuration of this pin.
Fixes: 8584d4fc ("ARM: dts: am335x-sl50: Add Toby-Churchill SL50 board support.")
Cc: <stable@vger.kernel.org> # 4.11
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Ethernet networking on K2L has been broken since v4.11-rc1. This was
caused by commit 32a34441a9 ("ARM: keystone: dts: fix netcp clocks
and add names"). This commit inadvertently moves on-chip static RAM
clock to the end of list of clocks provided for netcp. Since keystone
PM domain support does not have a list of recognized con_ids, only the
first clock in the list comes under runtime PM management. This means
the OSR (On-chip Static RAM) clock remains disabled and that broke
networking on K2L.
The OSR is used by QMSS on K2L as an external linking RAM. However this
is a standalone RAM that can be used for non-QMSS usage (as well as from
DSP side). So add a SRAM device node for the same and add the OSR clock
to the node.
Remove the now redundant OSR clock node from netcp.
To manage all clocks defined for netCP's use by runtime PM needs keystone
generic power domain (genpd) driver support which is under works.
Meanwhile, this patch restores K2L networking and is correct irrespective
of any future genpd work since OSR is an independent module and not part
of NetCP anyway.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
[nsekhar@ti.com: commit message updates, port to latest mainline]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Cc: stable@vger.kernel.org # for 4.11
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
We currently have three device nodes for the same USB hardware
block, as evident by the reuse of the same reg address multiple
times. Now that the chipidea driver fully supports OTG with the
MSM wrapper we can collapse the three nodes into one USB device
node, reflecting the true nature of the hardware.
Since we're here, we also mark the irq trigger flags correctly,
as IRQ_TYPE_LEVEL_HIGH instead of IRQ_TYPE_NONE.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Cc: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This USB controller has two phys, so add them both underneath the
ULPI bus, but only enable one of them based on the board
configuration. To get OTG to work, we need to add the id and vbus
detection info and also populate the regulators for the vbus
supply.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
