Commit Graph

12795 Commits

Author SHA1 Message Date
Christopher Staite
bb588820ef drm/radeon: fix MC blackout on evergreen+
Force the crtc mem requests on/off immediately rather
than waiting for the double buffered updates to kick in.
Seems we miss the update in certain conditions.  Also
handle the DCE6 case.

Signed-off-by: Christopher Staite <chris@yourdreamnet.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-01-27 22:38:43 -05:00
Paulo Zanoni
cb10799c19 drm/i915: turn on the power well before suspending
Our suspend code touches a lot of registers all over the place, so we
need to enable the power well before suspending.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Fixup compilation by stealing the header decl from the
dynamic power wells patch.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-28 00:26:10 +01:00
Paulo Zanoni
cc464b2a17 drm/i915: set TRANSCODER_EDP even earlier
Instead of setting it at the beginning of haswell_crtc_mode_set, let's
set it at the beginning of intel_crtc_mode_set. When
intel_crt_mode_set calls drm_vblank_pre_modeset we already need to
have the transcoder_edp correctly set, because eventually
drm_vblank_pre_modeset calls functions that call i915_pipe_enabled
from i915_irq.c, which will read PIPECONF(cpu_transcoder).

This is a bug that affects us since we added support for
TRANSCODER_EDP, but I was only able to see the problem after
suspending a machine with the power well disabled (got an "unclaimed
register" error.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-28 00:26:10 +01:00
Daniel Vetter
67c9640002 drm/i915: fixup per-crtc locking in intel_release_load_detect_pipe
One of the early return cases missed the mutex unlocking. Hilarity
ensued.

This regression has been introduced in

commit 7b24056be6
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Wed Dec 12 00:35:33 2012 +0100

    drm: don't hold crtc mutexes for connector ->detect callbacks

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59750
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: Cancan Feng <cancan.feng@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-01-28 07:31:59 +10:00
Paulo Zanoni
56e5a3f043 drm/i915: only disable enabled planes on intel_fb_restore_mode
We should avoid touching registers that are on the power down well
when we don't need to, because if we touch these registers when the
power well is disabled we'll get tons of "unclaimed register"
messages. This commit fixes some of these messages.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:56:16 +01:00
Paulo Zanoni
fa42e23c10 drm/i915: fix intel_init_power_wells
The current code was wrong in many different ways, so this is a full
rewrite. We don't have "different power wells for different parts of
the GPU", we have a single power well, but we have multiple registers
that can be used to request enabling/disabling the power well. So
let's be a good citizen and only use the register we're suppose to
use, except when we're loading the driver, where we clear the request
made by the BIOS.

If any of the registers is requesting the power well to be enabled, it
will be enabled. If none of the registers is requesting the power well
to be enabled, it will be disabled.

For now we're just forcing the power well to be enabled, but in the
next commits we'll change this.

V2:
  - Remove debug messages that could be misleading due to possible
    race conditions with KVMr, Debug and BIOS.
  - Don't wait on disabling: after a conversaion with a hardware
    engineer we discovered that the "restriction" on bit 31 is just
    for the "enable" case, and we don't even need to wait on the
    "disable" case.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:54:28 +01:00
Ville Syrjälä
80a75f7c44 drm/i915: SWF screatch registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:40:38 +01:00
Ville Syrjälä
56a12a5092 drm/i915: Include display_mmio_offset in sequencer index/data registers
SR01 needs to be touched to disable VGA on non-UMS setups too.
So the sequencer registers need to include the appripriate offset
on VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:32:03 +01:00
Ville Syrjälä
67cfc2032b drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLV
When passing the DP/HDMI/SDVO registers to the encoder init functions,
include the VLV specific offset in the value.

v2: Resolved conflicts w/ VLV SDVO elimination

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:31:43 +01:00
Ville Syrjälä
9d5f78fbbf drm/i915: VLV doesn't have SDVO
Don't call intel_sdvo_init() for VLV.

Preserve the same behaviour as when intel_sdvo_init() would
have returned false.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:31:13 +01:00
Ville Syrjälä
ca54b8107f drm/i915: Always use adpa_reg
Instead of using ADPA/VLV_ADPA/PCH_ADPA in various parts of
intel_crt code, just use adpa_reg which always contains the
correct value for the platform.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:29:52 +01:00
Ville Syrjälä
fc2de40986 drm/i915: PLL registers need an offset on VLV
v2: Dropped the clock gating registers

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:29:45 +01:00
Dave Airlie
483674325f Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel
Just a few small things:
- 2x workaround bits from Chris to fix up the new scanline waits enabled
  in 3.8 on snb. People who've been struck by this on dual-screen also
  need to upgrade the ddx.
- Dump the kernel version into i915_error_state, we've had a few mixups
  there recently.
- Disable gfx DMAR on gen4 devices, acked by David Woodhouse.

* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: dump UTS_RELEASE into the error_state
  iommu/intel: disable DMAR for g4x integrated gfx
  drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits
  drm/i915: Disable AsyncFlip performance optimisations
2013-01-26 18:17:39 +10:00
Greg Kroah-Hartman
422d26b6ec Merge 3.8-rc5 into driver-core-next
This resolves a gpio driver merge issue pointed out in linux-next.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-25 21:06:30 -08:00
Thierry Reding
d4ed60259e drm: Convert to devm_ioremap_resource()
Convert all uses of devm_request_and_ioremap() to the newly introduced
devm_ioremap_resource() which provides more consistent error handling.

devm_ioremap_resource() provides its own error messages so all explicit
error messages can be removed from the failure code paths.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Cc: David Airlie <airlied@linux.ie>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-25 12:21:46 -08:00
Shirish S
dda9012b2a drm/exynos: add check for the device power status
V2: Add mutex protection, while read.

The hdmi and mixer win_commit calls currently are
not checking the status of IP before updating the
respective registers, this patch adds this check.

Signed-off-by: Shirish S <s.shirish@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:46 +09:00
Sachin Kamat
428982e70a drm/exynos: Make 'drm_hdmi_get_edid' static
Fixes the following warning:
drivers/gpu/drm/exynos/exynos_drm_hdmi.c:111:13: warning:
symbol 'drm_hdmi_get_edid' was not declared. Should it be static?

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:46 +09:00
Arnd Bergmann
7cdc046d9e drm/exynos: fimd and ipp are broken on multiplatform
While the exynos DRM support in principle can work on
multiplatform, the FIMD and IPP sections of it both
include the plat/map-base.h header file, which is
not available on multiplatform. Rather than disabling
the entire driver, we can just conditionally build
these two parts.

Without this patch, building allyesconfig results in:

drivers/gpu/drm/exynos/exynos_drm_fimc.c:19:27: fatal error: plat/map-base.h: No such file or directory
drivers/gpu/drm/exynos/exynos_drm_ipp.c:20:27: fatal error: plat/map-base.h: No such file or directory

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2013-01-25 14:38:46 +09:00
Arnd Bergmann
05523d563d drm/exynos: don't include plat/gpio-cfg.h
Patch  9eb3e9e6f3 "drm/exynos: add support for ARCH_MULTIPLATFORM"
allowed building the exynos hdmi driver on non-samsung platforms,
which unfortunately broke compilation in combination with 22c4f42897
"drm: exynos: hdmi: add support for exynos5 hdmi", which added
an inclusion of the samsung-specific plat/gpio-cfg.h header file.

Fortunately, that header file is not required any more here, so
we can simply revert the inclusion in order to build the ARM
allyesconfig again without getting this error:

drivers/gpu/drm/exynos/exynos_hdmi.c:37:27: fatal error: plat/gpio-cfg.h: No such file or directory

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2013-01-25 14:38:45 +09:00
Sean Paul
77006a7ac8 drm/exynos: Remove "internal" interrupt handling
Remove the "internal" interrupt handling since it's never invoked and
remove "external" reference. This patch removes a bunch of dead code
and clarifies how hotplugging is handled in the HDMI driver.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:45 +09:00
Sachin Kamat
0315a902c0 drm/exynos: Add missing static specifiers in exynos_drm_rotator.c
Fixes the following warnings:
drivers/gpu/drm/exynos/exynos_drm_rotator.c:737:24: warning:
symbol 'rot_limit_tbl' was not declared. Should it be static?
drivers/gpu/drm/exynos/exynos_drm_rotator.c:754:27: warning:
symbol 'rotator_driver_ids' was not declared. Should it be static?

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:45 +09:00
Sean Paul
09760ea349 drm/exynos: Replace mdelay with usleep_range
Replace the unnecessary atomic mdelay calls with usleep_range calls.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:45 +09:00
Sachin Kamat
0bc4a0aa37 drm/exynos: Make ipp_handle_cmd_work static
Fixes the following warning:
drivers/gpu/drm/exynos/exynos_drm_ipp.c:872:6: warning:
symbol 'ipp_handle_cmd_work' was not declared. Should it be static?

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:44 +09:00
Sachin Kamat
b7848c7ad8 drm/exynos: Make g2d_userptr_get_dma_addr static
Fixes the following warning:
drivers/gpu/drm/exynos/exynos_drm_g2d.c:327:12: warning:
symbol 'g2d_userptr_get_dma_addr' was not declared. Should it be static?

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:44 +09:00
Inki Dae
b8b5c139ba drm/exynos: consider DMA_NONE flag to dmabuf import
This patch considers DMA_NONE flag for other drivers not using
dma mapping framework with iommu such as 3d gpu driver or others.

For example, there might be 3d gpu driver that has its own iommu
hw unit and iommu table mapping mechnism. So in this case,
the dmabuf buffer imported into this driver needs just only
sg table to map the buffer with its own iommu table itself.

So this patch makes dma_buf_map_attachment ignore dma_map_sg call
and just return sg table containing pages if dma_data_direction
is DMA_NONE.

Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2013-01-25 14:38:44 +09:00
Inki Dae
420ae1e262 drm/exynos: free sg object if dma_map_sg is failed
This patch releases sgt's sg object allocated by sgt_alloc_table
correctly.

When exynos_gem_map_dma_buf was called by dma_buf_map_attachmemt(),
the sgt's sg object was allocated by sg_alloc_tale() so
if dma_map_sg() is failed, the sg object should be released.

Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2013-01-25 14:38:44 +09:00
Seung-Woo Kim
e7808df1af drm/exynos: added validation of edid for vidi connection
If edid of vidi from user is invalid, size calculated from a number
of cea extensions can be wrong. So, validation should be checked.

Changelog v2:
- just code cleanup
  . declare raw_edid only if vidi->connection is enabled.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:43 +09:00
Rahul Sharma
9c08e4ba81 drm/exynos: let drm handle edid allocations
There's no need to allocate edid twice and do a memcpy when drm helpers
exist to do just that. This patch cleans that interaction up, and
doesn't keep the edid hanging around in the connector.

v4:
- removed error check for drm_mode_connector_update_edid_property
which is expected to fail for Virtual Connectors like VIDI.
Thanks to Seung-Woo Kim.

v3:
- removed MAX_EDID as it is not used anymore.

v2:
- changed vidi_get_edid callback inside vidi driver.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-01-25 14:38:43 +09:00
Ville Syrjälä
fba5d532d1 drm/i915: Set display_mmio_offset for VLV
This will cause display registers to include the correct
offset on VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:45:40 +01:00
Ville Syrjälä
d811215004 drm/i915: GPIO/GMBUS registers need an offset on VLV
GPIO/GMBUS registers must be offset on VLV, so simply
adjust gpio_mmio_base to include the correct offset.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:45:03 +01:00
Ville Syrjälä
54d9d493ce drm/i915: DPIO registers are VLV only and need an offset
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:42:29 +01:00
Ville Syrjälä
ff76301099 drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers
Instead of 0x18xxxx use (VLV_DISPLAY_BASE + xxxx).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:42:18 +01:00
Ville Syrjälä
07ec7ec55b drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
Instead of 0x18xxxx use (VLV_DISPLAY_BASE + xxxx).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:42:09 +01:00
Ville Syrjälä
d88b227086 drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:22:53 +01:00
Ville Syrjälä
4b0599854b drm/i915: Pipe palette registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:22:24 +01:00
Ville Syrjälä
4e8e7eb703 drm/i915: Pipe timing registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:13:13 +01:00
Ville Syrjälä
67d62c5746 drm/i915: PORT_HOTPLUG registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:08:25 +01:00
Ville Syrjälä
7e470abf54 drm/i915: Panel fitter registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:08:16 +01:00
Ville Syrjälä
b41fbda151 drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 23:02:30 +01:00
Ville Syrjälä
90f7da3fb5 drm/i915: DSPFW registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:59:41 +01:00
Ville Syrjälä
8f6d8ee9f6 drm/i915: VLV_DDL is VLV only and needs an offset
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:59:34 +01:00
Ville Syrjälä
9dc33f31f2 drm/i915: Cursor registers need an offset on VLV
CURSIZE is not present on VLV, so it was left out, as were the IVB
specific cursor B registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:54:53 +01:00
Ville Syrjälä
0c3870ee58 drm/i915: Pipe registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:53:25 +01:00
Ville Syrjälä
895abf0c3c drm/i915: Primary plane registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:44:17 +01:00
Ville Syrjälä
aab17139a0 drm/i915: PIPE M/N registers need an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:34:37 +01:00
Ville Syrjälä
b906487c51 drm/i915: VLV_VIDEO_DIP_CTL is for VLV only
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:29:40 +01:00
Ville Syrjälä
f12c47b279 drm/i915: Per-pipe PP registers are for VLV only
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:27:09 +01:00
Ville Syrjälä
f4ba9f8171 drm/i915: AUD_VID_DID needs an offset on VLV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:26:53 +01:00
Ville Syrjälä
10fce67a97 drm/i915: Add display_display_mmio_offset to intel_device_info
Add an optional offset to intel_device_info, which will added
to most display register offsets.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:26:42 +01:00
Ville Syrjälä
34f2be46c4 drm/i915: Convert intel_dp to enum port
Use intel_dig_port->port rather than intel_dp->output_reg.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-24 22:26:21 +01:00