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488 Commits

Author SHA1 Message Date
Xiaojie Yuan
87190edcf3 drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc header 
gc 10.1.2 introduced this new register

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
6d62290328 drm/amdgpu: add ip offset header for navi12 (v2) 
This adds the absolute offsets of each IP regiser block.

v2: Squash in MP1 update

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
Jay Cornwall
5145d57ec5 drm/amdkfd: Extend CU mask to 8 SEs (v3) 
Following bitmap layout logic introduced by:
"drm/amdgpu: support get_cu_info for Arcturus".

v2: squash in fixup for gfx_v9_0.c (Alex)
v3: squash in debug print output fix

Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:19:11 -05:00
Kent Russell
57d352f769 drm/amdgpu: Update NBIO headers to add TXCLK3/4 
These are added for VG20, and are needed for PCIe bandwidth.

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:18:50 -05:00
Dennis Li
4bb6b8c758 drm/amd/include: add define of TCP_EDC_CNT_NEW 
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-31 14:50:54 -05:00
Dennis Li
ca3f422f53 drm/amd/include: add bitfield define for EDC registers 
Add EDC registers to support VEGA20 RAS

Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-31 14:50:47 -05:00
Hawking Zhang
03c9963f47 drm/amdgpu: add umc v6_1_1 IP headers 
the change introduces IP headers for unified memory controller (umc)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-31 14:49:10 -05:00
Hawking Zhang
245219a660 drm/amdgpu: add rsmu v_0_0_2 ip headers 
remote smu (rsmu) is a sub-block used as ip register interface,
error handling, reset generation.etc

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-31 14:49:03 -05:00
Evan Quan
9829e3d89b drm/amd/powerplay: add new sensor type for VCN powergate status 
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-30 23:48:34 -05:00
Le Ma
9d4d7236ef drm/amd/include: adjust base offset of SMUIO and THM for Arcturus 
Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source
files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20
reusable for Arcturus, align this base offset with Vega20.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-30 23:48:34 -05:00
Evan Quan
4c35e77865 drm/amd/powerplay: add smcdpminfo table v4_6 support 
New smcdpminfo table used in arcturus.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-30 23:48:33 -05:00
Alex Deucher
a2c28e34f8 drm/amdgpu/powerplay: add a new interface to set the mp1 state 
This is required for certain cases such as various GPU resets
(mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into
the appropriate state for when the hw is re-initialized.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-30 23:24:21 -05:00
Jonathan Kim
c52e7ebce7 drm/amdgpu: exposing fica registers to df offsets 
exposing fica registers to poll df pie data for xgmi error counters for
vega20.

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:07 -05:00
Evan Quan
7e01a2ec96 drm/amd/powerplay: correct SW SMU valid mapping check 
Current implementation is not actually able to detect
invalid message/table/workload mapping.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:07 -05:00
James Zhu
8a6fcd3532 drm/amdgpu/: add clientID for 2nd vcn instance 
add clientID for 2nd vcn instance, remove unused SOC15_IH_CLIENTID_SYSHUB.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:05 -05:00
Le Ma
7d19b15f70 drm/amdgpu: add VMC1 interrupt client id for Arcturus 
New IH client id for VMC1.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
8024f1d5e1 drm/amdgpu: add SDMA 2~7 interrupt client id for Arcturus 
Add new client ids.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:02 -05:00
Le Ma
f1cf876931 drm/amdgpu: add Arcturus ip_offset header (v3) 
Provides the absolute offsets of the IP register
blocks.

v2: update chip name in source code
v3: squash in MP offset updates (Alex)

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Leo Liu
c54a60db0d drm/amdgpu: add VCN2.5 headers 
VCN is the multi-media block.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Le Ma
4f727ecefe drm/amdgpu: add sdma 4.2.2 header files for Arcturus 
SDMA is the system DMA block.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Le Ma
0e96cf7f67 drm/amdgpu: add mmhub 9.4.1 header files for Acrturus 
mmhub is the GPU memory hub used by SDMA and VCN.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Xiaojie Yuan
a0f6d926f1 drm/amdgpu/soc15: initialize reg base for navi14 (v2) 
Initialize the IP register base offsets for navi14.

v2: squash in MP, CLK, THM updates

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:58 -05:00
Evan Quan
617a64dc85 drm/amd/powerplay: increase the SMU msg response waiting time 
This is expected to fix some mode1 reset failures. And this
affects SMU part only as the timeout setting for other parts
is controlled by a different macro.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-11 14:37:23 -05:00
Huang Rui
a201b6ac20 drm/amd/powerplay: make athub pg bit configured by pg_flags 
The athub pg features enabling should be indicated by pg_flags.

Reported-by: Lijo Lazar <Lijo.Lazar@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-25 13:54:32 -05:00
Charlene Liu
bb21290ff6 drm/amd/display: Create DWB resource for DCN2 
[Description]
dcn20 has num_dwb =1 in the res cap, but not created.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Duke Du <Duke.Du@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-22 09:34:11 -05:00
Jack Xiao
886f82aa7a drm/amdgpu/mes10.1: add ip block mes10.1 (v2) 
MES takes over the scheduling capability of GFX and SDMA,
add MES as a standalone ip.

v2: squash in updates (Alex)

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:58:22 -05:00
Xiaojie Yuan
6a8ee0257d drm/amdgpu/discovery: update definition for struct die_header 
Update to latest spec.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:58:21 -05:00
Xiaojie Yuan
70cbfe3d64 drm/amdgpu/discovery: add harvest info data table 
Add support for the harvest tables.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:58:21 -05:00
Xiaojie Yuan
478586d6d5 drm/amdgpu/discovery: update definitions of table_info and binary_header 
Use the proper definitions.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:58:21 -05:00
Xiaojie Yuan
f39f5bb1c9 drm/amdgpu/discovery: add ip discovery initial support 
The IP discovery table lists is populated by the psp at power on
and includes all of the hw details on the board:
- List of IPs and MMIO offsets
- IP harvest details
- IP configuration details

v2: prefix struct and function names with 'amdgpu'
v3: read table binary from vram using mmMM_INDEX and mmMM_DATA
    update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR)
    add 'instance_number' field per ip info
    consider endianness and replace uint8/16/32_t with u8/16/32
    initialize register base addresses
    initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw
    get major and minor version using a single api
    don't expose internal data structures in amdgpu_discovery.h
v4: RCC_CONFIG_MEMSIZE is in MB units
    hold mmio_idx_lock while reading ip discovery binary
v5: pick out discovery.h as a cross-OS header
    do structure pointer cast directly
    consider endianness while using the member of structure
    convert base addresses to dword

at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the
top of the frame buffer (just below the reserved regions for PSP & SMU).

ip discovery data table includes the collection of each ip's identification
number, base addresses, version number, and harvest setting placeholder.

gc data table includes gfx info structure.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:58:21 -05:00
Hawking Zhang
5527cd0640 drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/ 
interrupt source packet definitions for the display block (DCN).

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:30 -05:00
Hawking Zhang
abade675e0 drm/amdgpu: add irq sources for vcn v2_0 (v2) 
Add the interrupt source packet definitions.

v2: update (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:30 -05:00
Hawking Zhang
4984dd069f drm/amdgpu: add irq sources for sdma v5_0 
Add the interrupt source packet definitions.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
cb3908c133 drm/amdgpu: add irq sources for gfx v10_1 
Add the interrupt source packet definitions.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Jack Xiao
367adb2ad5 drm/amdgpu/athub2: enable athub2 clock gating 
Enable athub2 clock gating and light sleep

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:35:29 -05:00
Hawking Zhang
9faa494e2f drm/amdgpu: add flag to support IH clock gating 
Add new flag for IH (interrupt handler) clockgating.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:25:52 -05:00
Hawking Zhang
714ff85251 drm/amdgpu: add new HDP CG flags 
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/
DS (Deep Sleep)/SD (Shut Down) modes are supported. However,
only one of these modes can be enabled at one time.

There is no dynamic power mode switch support. clock/power gating
has to be disabled before making any power mode change.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:25:46 -05:00
Huang Rui
a9833d02b5 drm/amdgpu: add v10 structs header (v2) 
Header for CP structures (MQD, etc.)

V2: squash in updates

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 21:16:37 -05:00
Hawking Zhang
33934b3576 drm/amdgpu: add navi10 ip offset header 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:53 -05:00
Hawking Zhang
10e4b22735 drm/amdgpu: atomfirmware.h updates for navi10 
Updated tables for Navi10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:48 -05:00
Hawking Zhang
efd8725f03 drm/amdgpu: add navi10 enums header 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:46 -05:00
Hawking Zhang
d2996831b2 drm/amdgpu: add SMUIO 11.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:44 -05:00
Hawking Zhang
3d220cc3bd drm/amdgpu: add OSS 5.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:42 -05:00
Hawking Zhang
f519f0be45 drm/amdgpu: add MMHUB 2.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:39 -05:00
Hawking Zhang
be4008b8c5 drm/amdgpu: add GC 10.1 register headers (v4) 
v2: Update regs (Alex)
v3: More updates (Alex)
v4: more updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:35 -05:00
Hawking Zhang
326354fa97 drm/amdgpu: add VCN 2.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:33 -05:00
Hawking Zhang
9edefe7bac drm/amdgpu: add NBIO 2.3 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:31 -05:00
Hawking Zhang
d33ad04027 drm/amdgpu: add MP 11.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:28 -05:00
Hawking Zhang
2a3196f1f0 drm/amdgpu: add HDP 5.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:26 -05:00
Hawking Zhang
d6ad5023e8 drm/amdgpu: add DCN 2.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:23 -05:00