Katsuhiro Suzuki
6c264416c9
clk: uniphier: add video input subsystem clock
...
Add a clock for video input subsystem (EXIV) on
UniPhier LD11/LD20 SoCs.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com >
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-08-31 18:41:14 -07:00
Katsuhiro Suzuki
e3dd205860
clk: uniphier: add audio system clock
...
Add clock for audio subsystem (AIO) and SoC internal audio codec
(EVEA) on UniPhier LD11/LD20 SoCs.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com >
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-08-31 18:40:23 -07:00
Masahiro Yamada
736de651a8
clk: uniphier: add PXs3 clock data
...
Add basic clock data for Socionext's new SoC PXs3.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-08-31 18:34:35 -07:00
Kunihiko Hayashi
9959989fc4
clk: uniphier: add ethernet clock control support
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Add clock control for ethernet controller on Pro4, PXs2, LD11 and LD20.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com >
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-08-30 22:29:29 -07:00
Masahiro Yamada
e66d57a92e
clk: uniphier: remove sLD3 SoC support
...
This SoC is too old. It is difficult to maintain any longer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Acked-by: Rob Herring <robh@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-08-03 15:38:14 -07:00
Masahiro Yamada
72d0d8672c
clk: uniphier: provide NAND controller clock rate
...
This allows the NAND driver to get the clock rate via clk_get_rate().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-06-21 10:47:27 -07:00
Masahiro Yamada
2a3532214e
clk: uniphier: add eMMC clock for LD11 and LD20 SoCs
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Add clock for the Cadence eMMC controller on LD11/LD20.
For the other SoCs, the clock for the eMMC controller is included
in the MIO/SD control block.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-02-03 11:55:21 -08:00
Masahiro Yamada
19771622d8
clk: uniphier: add NAND clock for all UniPhier SoCs
...
Add clock line for the Denali NAND controller.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2017-02-03 11:55:20 -08:00
Masahiro Yamada
1221ae211f
clk: uniphier: add cpufreq data for LD11, LD20 SoCs
...
Add more data to 64bit SoCs for the cpufreq support.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2016-12-07 16:17:03 -08:00
Masahiro Yamada
7f4d3b52b6
clk: uniphier: add clock data for UniPhier SoCs
...
Add clock data arrays for all UniPhier SoCs with a binding document.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Acked-by: Rob Herring <robh@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org >
2016-09-16 16:31:38 -07:00
