Jani Nikula
85b17e6e4d
drm/i915: clean up virtual PCH special case handling
...
Use intel_pch_type() also for mapping the no PCH case (PCH id 0) to
PCH_NONE to simplify code.
Also make sure that intel_pch_type() knows all the PCH ids returned by
intel_virt_detect_pch(). Loudly fail if this isn't the case; this
shouldn't happen anyway.
Cc: Colin Xu <Colin.Xu@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Tested-by: Colin Xu <Colin.Xu@intel.com >
Reviewed-by: Colin Xu <Colin.Xu@intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180608123330.31003-4-jani.nikula@intel.com
2018-06-11 10:21:12 +03:00
Lucas De Marchi
b8bf31d82d
drm/i915: document PCH_NOP
...
There's a difference between PCH_NONE and PCH_NOP: the former means we
don't have a PCH while in the latter we do, but it doesn't have the
south display.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180608123330.31003-3-jani.nikula@intel.com
2018-06-11 10:21:08 +03:00
Jani Nikula
78ef3faff9
drm/i915: fix guest virtual PCH detection on non-PCH systems
...
Virtualized non-PCH systems such as Broxton or Geminilake should use
PCH_NONE to indicate no PCH rather than PCH_NOP. The latter is a
specific case to indicate a PCH system without south display.
Reported-by: Colin Xu <Colin.Xu@intel.com >
Cc: Colin Xu <Colin.Xu@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Tested-by: Colin Xu <Colin.Xu@intel.com >
Reviewed-by: Colin Xu <Colin.Xu@intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180608123330.31003-2-jani.nikula@intel.com
2018-06-11 10:21:04 +03:00
Xinyun Liu
1417fad75c
drm/i915/gvt: use array to avoid potential buffer overflow
...
Array 'pdp_pair' of size 1 may use index value(s) 1..7.
Changed to pdps[8] to avoid confusion.
Signed-off-by: Xinyun Liu <xinyun.liu@intel.com >
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com >
2018-06-11 15:04:45 +08:00
Xinyun Liu
659571953d
drm/i915/gvt: removed unnecessary boundary check
...
type is already checked in the function entry. So it is unnecessary
to check it again.
Signed-off-by: Xinyun Liu <xinyun.liu@intel.com >
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com >
2018-06-11 15:04:32 +08:00
Xinyun Liu
1f1c60d5b5
drm/i915/gvt: Avoid dereference a potential null pointer
...
Add sanity check for up_irq_info.
Signed-off-by: Xinyun Liu <xinyun.liu@intel.com >
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com >
2018-06-11 15:03:36 +08:00
Chris Wilson
eed2890374
drm/i915/gtt: Reorder aliasing_ppgtt fini
...
To allow ourselves to use a first class vma for the aliasing_ppgtt page
directory, we have to reorder the shutdown on module unload to remove
and unpin the aliasing_ppgtt before complaining about any objects left
in the GGTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180609090151.22007-1-chris@chris-wilson.co.uk
2018-06-09 10:37:58 +01:00
Chris Wilson
e1f8789883
drm/i915/gtt: Remove vgpu check for gen6
...
Since vgpu is not supported on Haswell or any other gen6/7, we do not
need to check and act upon it's enablement.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180608150435.15010-2-chris@chris-wilson.co.uk
2018-06-08 19:30:03 +01:00
Chris Wilson
f6b1e35f3e
drm/i915/gtt: Remove redundant hsw_mm_switch()
...
hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the
redundant specialism.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180608150435.15010-1-chris@chris-wilson.co.uk
2018-06-08 19:30:02 +01:00
Chris Wilson
b4e2727df2
drm/i915/gtt: Fix unwind length passed to gen6_ppgtt_clear_range
...
When we want to unwind an error when allocating the PD for gen6, we call
gen6_ppgtt_clear_range() telling to clear upto the PD we've previously
allocated. However, we passed it an incorrect length, passing it the
endpoint instead. Fortunately, as the start was always 0, this has no
impact today, but tomorrow we want to start using non-zero origins.
Reported-by: Matthew Auld <matthew.william.auld@gmail.com >
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180608173221.10455-1-chris@chris-wilson.co.uk
2018-06-08 19:29:24 +01:00
Ville Syrjälä
672b3c4bc3
drm/i915: Fix sprite destination colorkeying on SKL+
...
On SKL+ the dst colorkey must be configured on the lower
plane that contains the colorkey. This is in contrast to
most earlier platforms where the dst colorkey is configured
on the plane above.
The hardware will peform dst keying only between two immediately
adjacent (in zorder) planes. Plane 2 will be keyed against plane 1,
plane 3 againts plane 2, and so on. There is no way to key arbitrary
planes against plane 1. Thus offering dst color keying on plane 3+
is pointless. In fact it can be harmful since enabling dst keying on
more than one plane on the same pipe leads to only the top-most of
the planes performing the keying. For any plane lower in zorder the
dst key enable is simply ignored.
v2: s/plane 0/plane 1/ etc. since the hw plane names start from 1
Don't break dst colorkey on pre-SKL sprites (hunk ended in the
wrong patch)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180529182804.8571-1-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com > #v1
2018-06-08 21:20:21 +03:00
Chris Wilson
51e645b665
drm/i915: Mark the GPU as wedged without error on fault injection
...
If we have been instructed (by CI) to inject a fault to load the module
with a wedged GPU, do so quietly less we upset CI.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Michał Winiarski <michal.winiarski@intel.com >
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com >
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180607134558.31150-1-chris@chris-wilson.co.uk
2018-06-08 10:36:10 +01:00
Mika Kuoppala
39e78234b0
drm/i915: Add WaKBLVECSSemaphoreWaitPoll
...
There is a problem with kbl up to rev E0 where a heavy
memory/fabric traffic from adjacent engine(s) can cause an engine
reset to fail. This traffic can be from normal memory accesses
or it can be from heavy polling on a semaphore wait.
For engine hogging causing a fail, we already fallback to
full reset. Which effectively stops all engines and thus
we only add a workaround documentation.
For the semaphore wait loop poll case, we add one microsecond
poll interval to semaphore wait to guarantee bandwidth for
the reset preration. The side effect is that we make semaphore
completion latencies also 1us longer.
v2: Let full reset handle the adjacent engine idling (Chris)
v3: Skip render engine (Joonas), please checkpatch on define (Mika)
References: https://bugs.freedesktop.org/show_bug.cgi?id=106684
References: VTHSD#2227190, HSDES#1604216706, BSID#0917
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Acked-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180607172444.17080-1-mika.kuoppala@linux.intel.com
2018-06-08 12:16:20 +03:00
Mika Kuoppala
c30acb04e7
drm/i915: Cancel reset preparations on failed resets
...
Our reset handling has a retry layer further up in the
chain. As we have told the engine to prepare for reset,
and failed it, make sure to remove that preparation so
that the next attempted reset has a clean slate by triggering
another full prepare cycle for the engines.
v2: ret as int, simplified cleanup (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605160357.32591-1-mika.kuoppala@linux.intel.com
2018-06-08 12:16:19 +03:00
Chris Wilson
17f297b427
drm/i915/gtt: Push allocation to hw ppgtt constructor
...
In the next patch, we will subclass the gen6 hw_ppgtt. In order, for the
two different generations of hw ppgtt stucts to be of different size,
push the allocation down to the constructor.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180607163040.9781-1-chris@chris-wilson.co.uk
2018-06-07 21:53:13 +01:00
Chris Wilson
93f2cde2a4
drm/i915: Decouple vma vfuncs from vm
...
To allow for future non-object backed vma, we need to be able to
specialise the callbacks for binding, et al, the vma. For example,
instead of calling vma->vm->bind_vma(), we now call
vma->ops->bind_vma(). This gives us the opportunity to later override the
operation for a custom vma.
v2: flip order of unbind/bind
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180607154047.9171-2-chris@chris-wilson.co.uk
2018-06-07 21:53:11 +01:00
Chris Wilson
520ea7c581
drm/i915: Prepare for non-object vma
...
In order to allow ourselves to use VMA to wrap other entities other than
GEM objects, we need to allow for the vma->obj backpointer to be NULL.
In most cases, we know we are operating on a GEM object and its vma, but
we need the core code (such as i915_vma_pin/insert/bind/unbind) to work
regardless of the innards.
The remaining eyesore here is vma->obj->cache_level and related (but
less of an issue) vma->obj->gt_ro. With a bit of care we should mirror
those on the vma itself.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180607154047.9171-1-chris@chris-wilson.co.uk
2018-06-07 21:53:10 +01:00
Jani Nikula
807cba6559
Merge tag 'gvt-fixes-2018-04-19' of https://github.com/intel/gvt-linux into drm-intel-next-fixes
...
gvt-fixes-2018-04-19
- cmd parser error path mem leak fix (Colin)
- fix dp aux header validation (Changbin)
- sanity check on pfn after vfio pin page (Changbin)
- fix msi eventfd put (Xiong)
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180419073948.4mojv7xaxxvfuyud@zhen-hp.sh.intel.com
2018-06-07 12:06:07 +03:00
Mahesh Kumar
197af5f213
drm/i915/icl: Don't update enabled dbuf slices struct until updated in hw
...
Do not update number of enabled dbuf slices in dev_priv struct until we
actually enable/disable dbuf slice in hw. This is leading to never
updating dbuf slices and resulting in DBuf slice mismatch warning.
Fixes: aa9664ffe8paulo.r.zanoni@intel.com >
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180517132626.5885-1-mahesh1.kumar@intel.com
(cherry picked from commit 6ceb727717jani.nikula@intel.com >
2018-06-07 11:39:15 +03:00
Mahesh Kumar
2f08b23d70
drm/i915/icl: fix icl_unmap/map_plls_to_ports
...
All connectors may not have best_encoder attached, so don't dereference
encoder pointer for each connector.
Fixes: c27e917e2blucas.demarchi@intel.com >
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180525155238.7054-1-lucas.demarchi@intel.com
(cherry picked from commit c46ef57d20jani.nikula@intel.com >
2018-06-07 11:39:05 +03:00
Ville Syrjälä
47541443a6
drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup
...
We already handle the color encoding mode properly. Remove the broken
NV12 special case.
Cc: Vidya Srinivas <vidya.srinivas@intel.com >
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com >
Fixes: 8ed30ab6acville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180521185613.5097-1-ville.syrjala@linux.intel.com
Reviewed-By: Vidya Srinivas <vidya.srinivas@intel.com >
(cherry picked from commit 012d79e6a3jani.nikula@intel.com >
2018-06-07 11:39:01 +03:00
Chris Wilson
521370106d
drm/i915: Change i915_gem_fault() to return vm_fault_t
...
In preparation for vm_fault_t becoming a distinct type, convert the
fault handler (i915_gem_fault()) over to the new interface.
Based on a patch by Souptick Joarder
References: 1c8f422059chris@chris-wilson.co.uk >
Cc: Souptick Joarder <jrdr.linux@gmail.com >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180606214520.20220-1-chris@chris-wilson.co.uk
2018-06-07 08:46:04 +01:00
Chris Wilson
8571a05a9d
drm/i915: Use GEM suspend when aborting initialisation
...
As part of our GEM initialisation now, we send a request to the hardware
in order to record the initial GPU state. This coupled with deferred
idle workers, makes aborting on error tricky. We already have the
mechanism in place to wait on the GPU and cancel all the deferred
workers for suspend, so let's reuse it during the error teardown. It is
already used in places for later init error handling, but doing so at
this point is slightly ugly due to the mutex dance (it's ok, the module
load is still single threaded).
Testcase: igt/drv_module_reload/basic-reload-inject
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Michał Winiarski <michal.winiarski@intel.com >
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180606145441.4460-1-chris@chris-wilson.co.uk
2018-06-07 08:42:36 +01:00
Zhenyu Wang
0766e2efc6
Merge tag 'drm-intel-next-2018-06-06' into gvt-next
...
Backmerge for recent request->hw_context change and
new vGPU huge page capability definition.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com >
2018-06-07 10:24:50 +08:00
Rodrigo Vivi
14c3f84250
drm/i915: Update DRIVER_DATE to 20180606
...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
2018-06-06 15:10:47 -07:00
Chris Wilson
64b3c93649
drm/i915/gtt: Fix typo in fill_px() macro
...
The macro declared the ppgtt parameter but implicitly used the local vm
instead.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180606205128.25952-1-chris@chris-wilson.co.uk
2018-06-06 22:49:34 +01:00
Chris Wilson
cf68f0c3a0
drm/i915: Mark i915.inject_load_failure as being hit
...
When we reach the magic value and do inject a fault into our module load,
mark the module option as being hit. Since we fail from inside pci
probe, the module load isn't actually aborted and the module (and
parameters) are left lingering. igt can then inspect the parameter on its
synchronous completion of modprobe to see if the fault injection was
successful, and will keeping on injecting new faults until the module
succeeds in loading having surpassed the number of fault points.
v2: Reset to 0 after being hit;
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Michał Winiarski <michal.winiarski@intel.com >
Cc: Imre Deak <imre.deak@intel.com >
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com >
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180606144153.4244-1-chris@chris-wilson.co.uk
2018-06-06 18:37:30 +01:00
Linus Torvalds
135c5504a6
Merge tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm
...
Pull drm updates from Dave Airlie:
"This starts to support NVIDIA volta hardware with nouveau, and adds
amdgpu support for the GPU in the Kabylake-G (the intel + radeon
single package chip), along with some initial Intel icelake enabling.
Summary:
New Drivers:
- v3d - driver for broadcom V3D V3.x+ hardware
- xen-front - XEN PV display frontend
core:
- handle zpos normalization in the core
- stop looking at legacy pointers in atomic paths
- improved scheduler documentation
- improved aspect ratio validation
- aspect ratio support for 64:27 and 256:135
- drop unused control node code.
i915:
- Icelake (ICL) enabling
- GuC/HuC refactoring
- PSR/PSR2 enabling and fixes
- DPLL management refactoring
- DP MST fixes
- NV12 enabling
- HDCP improvements
- GEM/Execlist/reset improvements
- GVT improvements
- stolen memory first 4k fix
amdgpu:
- Vega 20 support
- VEGAM support (Kabylake-G)
- preOS scanout buffer reservation
- power management gfxoff support for raven
- SR-IOV fixes
- Vega10 power profiles and clock voltage control
- scatter/gather display support on CZ/ST
amdkfd:
- GFX9 dGPU support
- userptr memory mapping
nouveau:
- major refactoring for Volta GV100 support
tda998x:
- HDMI i2c CEC support
etnaviv:
- removed unused logging code
- license text cleanups
- MMU handling improvements
- timeout fence fix for 50 days uptime
tegra:
- IOMMU support in gr2d/gr3d drivers
- zpos support
vc4:
- syncobj support
- CTM, plane alpha and async cursor support
analogix_dp:
- HPD and aux chan fixes
sun4i:
- MIPI DSI support
tilcdc:
- clock divider fixes for OMAP-l138 LCDK board
rcar-du:
- R8A77965 support
- dma-buf fences fixes
- hardware indexed crtc/du group handling
- generic zplane property support
atmel-hclcdc:
- generic zplane property support
mediatek:
- use generic video mode function
exynos:
- S5PV210 FIMD variant support
- IPP v2 framework
- more HW overlays support"
* tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm: (1286 commits)
drm/amdgpu: fix 32-bit build warning
drm/exynos: fimc: signedness bug in fimc_setup_clocks()
drm/exynos: scaler: fix static checker warning
drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC
drm/amd/display: Remove use of division operator for long longs
drm/amdgpu: Update GFX info structure to match what vega20 used
drm/amdgpu/pp: remove duplicate assignment
drm/sched: add rcu_barrier after entity fini
drm/amdgpu: move VM BOs on LRU again
drm/amdgpu: consistenly use VM moved flag
drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories
drm/amdgpu: further optimize amdgpu_vm_handle_moved
drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2
drm/amdgpu: rework VM state machine lock handling v2
drm/amdgpu: Add runtime VCN PG support
drm/amdgpu: Enable VCN static PG by default on RV
drm/amdgpu: Add VCN static PG support on RV
drm/amdgpu: Enable VCN CG by default on RV
drm/amdgpu: Add static CG control for VCN on RV
drm/exynos: Fix default value for zpos plane property
...
2018-06-06 08:16:33 -07:00
Chris Wilson
82ad6443a5
drm/i915/gtt: Rename i915_hw_ppgtt base member
...
In the near future, I want to subclass gen6_hw_ppgtt as it contains a
few specialised members and I wish to add more. To avoid the ugliness of
using ppgtt->base.base, rename the i915_hw_ppgtt base member
(i915_address_space) as vm, which is our common shorthand for an
i915_address_space local.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605153758.18422-1-chris@chris-wilson.co.uk
2018-06-05 21:11:20 +01:00
Chris Wilson
cd68e04cf5
drm/i915/error: Fixup inactive/active counting
...
The inactive counter was over the active list, and vice versa.
Fortuitously this should not cause a problem in practice as they shared
the same array and clamped the number of entries they would write.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605160623.30163-1-chris@chris-wilson.co.uk
2018-06-05 19:23:33 +01:00
Michal Wajdeczko
70be8b3dab
drm/i915/guc: Don't leak stage descriptor pool on init failure
...
In case of failure during GuC clients creation, we forget to
cleanup earlier pool allocation. Use proper teardown to fix that.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com >
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Michal Winiarski <michal.winiarski@intel.com >
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com >
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605120547.16468-1-michal.wajdeczko@intel.com
2018-06-05 19:21:51 +01:00
Tvrtko Ursulin
9f473ecfe7
drm/i915/pmu: Do not assume fixed hrtimer period
...
As Chris has discovered on his Ivybridge, and later automated test runs
have confirmed, on most of our platforms hrtimer faced with heavy GPU load
can occasionally become sufficiently imprecise to affect PMU sampling
calculations.
This means we cannot assume sampling frequency is what we asked for, but
we need to measure the interval ourselves.
This patch is similar to Chris' original proposal for per-engine counters,
but instead of introducing a new set to work around the problem with
frequency sampling, it swaps around the way internal frequency accounting
is done. Instead of accumulating current frequency and dividing by
sampling frequency on readout, it accumulates frequency scaled by each
period.
v2:
* Typo in commit message, comment on period calculation and USEC_PER_SEC.
(Chris Wilson)
Testcase: igt/perf_pmu/*busy* # snb, ivb, hsw
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com >
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605140253.3541-1-tvrtko.ursulin@linux.intel.com
2018-06-05 16:45:01 +01:00
Tvrtko Ursulin
57d7116c47
drm/i915/trace: Context field needs to be 64-bit wide
...
Underlaying field is u64 so the tracepoint needs to be as well.
v2:
* Re-order binary packet for 64-bit alignment. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com >
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605134124.25672-1-tvrtko.ursulin@linux.intel.com
2018-06-05 16:44:12 +01:00
Tvrtko Ursulin
f24e74a7b7
drm/i915/trace: Remove engine out of the context sandwich
...
In the string tracepoint representation we ended up with the engine
sandwiched between context hardware id and context fence id.
Move the two pieces of context data together for redability.
Binary records are left as is, that is both fields remaing under the
existing name and ordering.
v2:
* Do not consolidate the printk format, just reorder. (Lionel)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com >
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180525082642.18246-2-tvrtko.ursulin@linux.intel.com
2018-06-05 16:44:12 +01:00
Tvrtko Ursulin
2956e970f0
drm/i915/trace: Describe engines as class:instance pairs
...
Instead of using the engine->id, use uabi_class:instance pairs in trace-
points including engine info.
This will be more readable, more future proof and more stable for
userspace consumption.
v2:
* Use u16 for class and instance. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com >
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Cc: svetlana.kukanova@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180525082642.18246-1-tvrtko.ursulin@linux.intel.com
2018-06-05 16:44:11 +01:00
Chris Wilson
420980ca79
drm/i915: Swap magics and use SZ_1M
...
Since the kernel provides SZ_1M, use it in preference of 1 << 20.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605135746.8020-1-chris@chris-wilson.co.uk
2018-06-05 16:16:41 +01:00
Michal Wajdeczko
b96f6ebfd0
drm/i915: Correctly handle error path in i915_gem_init_hw
...
In function gem_init_hw() we are calling uc_init_hw() but in case
of error later in function, we missed to call matching uc_fini_hw()
v2: pulled out from the series
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com >
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com >
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605122443.23776-1-michal.wajdeczko@intel.com
2018-06-05 15:16:08 +01:00
Chris Wilson
83d317adfb
drm/i915/vma: Move the bind_count vs pin_count assertion to a helper
...
To spare ourselves a long line later, refactor the repeated check of
bind_count vs pin_count to a helper.
v2: Fix up the commentary!
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605094107.31367-1-chris@chris-wilson.co.uk
2018-06-05 15:16:07 +01:00
Chris Wilson
744799850e
drm/i915/gtt: Teach restore-gtt to walk the ggtt vma list not the object list
...
In preparation, for having non-vma objects stored inside the ggtt, to
handle restoration of the GGTT following resume, we need to walk over
the ggtt address space rebinding vma, as opposed to walking over bound
objects looking for ggtt entries.
v2: Skip objects only bound for the aliasing_ppgtt
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com > #v1
Link: https://patchwork.freedesktop.org/patch/msgid/20180605082856.19221-1-chris@chris-wilson.co.uk
2018-06-05 15:16:07 +01:00
Chris Wilson
d901e8e673
drm/i915/ringbuffer: Make context pin/unpin symmetric
...
Currently, we have a special routine for pinning the context state at
the start of activity tracking, but lack the complementary unpin
routine. Create it to to ease later patches that want to do partial
teardown on error, and, not least, to improve the readability of the
code.
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180605085348.3018-1-chris@chris-wilson.co.uk
2018-06-05 15:16:07 +01:00
Changbin Du
52b2416ceb
drm/i915: Add new vGPU cap info bit VGT_CAPS_HUGE_GTT
...
This adds a new vGPU cap info bit VGT_CAPS_HUGE_GTT, which is to detect
whether the host supports shadowing of huge gtt pages. If host does
support it, remove the page sizes restriction for vGPU.
Signed-off-by: Changbin Du <changbin.du@intel.com >
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/1525770425-5373-1-git-send-email-changbin.du@intel.com
2018-06-05 16:57:01 +03:00
Mahesh Kumar
6ceb727717
drm/i915/icl: Don't update enabled dbuf slices struct until updated in hw
...
Do not update number of enabled dbuf slices in dev_priv struct until we
actually enable/disable dbuf slice in hw. This is leading to never
updating dbuf slices and resulting in DBuf slice mismatch warning.
Fixes: aa9664ffe8paulo.r.zanoni@intel.com >
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180517132626.5885-1-mahesh1.kumar@intel.com
2018-06-04 16:53:55 -07:00
Lionel Landwerlin
61d5676b55
drm/i915/perf: fix ctx_id read with GuC & ICL
...
One thing we didn't really understand about the OA report is that the
ContextID field (dword 2) is copy of the context descriptor (dword 1).
On Gen8->10 and without using GuC we didn't notice the issue because
we only checked the 21bits of the ContextID field in the OA reports
which matches exactly the hw_id stored into the context descriptor.
When using GuC submission we have an issue of a non matching hw_id
because GuC uses bit 20 of the hw_id to signal proxy submission. This
change introduces a mask to compare only the relevant bits.
On ICL the context descriptor format has changed and we failed to
address this. On top of using a mask we also need to shift the bits
properly.
v2: Reuse lrc_desc rather than recomputing part of it (Chris/Michel)
v3: Always pin the context we're filtering with (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 1de401c08fhttps://bugs.freedesktop.org/show_bug.cgi?id=104252
BSpec: 1237
Testcase: igt/perf/gen8-unprivileged-single-ctx-counters
Acked-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Michel Thierry <michel.thierry@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180602112946.30803-3-lionel.g.landwerlin@intel.com
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: Matthew Auld <matthew.auld@intel.com >
Cc: Jani Nikula <jani.nikula@linux.intel.com >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com >
Cc: intel-gfx@lists.freedesktop.org
2018-06-04 18:16:08 +01:00
Lionel Landwerlin
218b500098
drm/i915: drop one bit on the hw_id when using guc
...
We currently using GuC as a proxy to the hardware. When Guc is used in
such mode, it consumes the bit 20 of the hw_id to indicate that the
workload was submitted by proxy.
So far we probably haven't seen the issue because we need to allocate
1048576+ contexts to hit this issue. Still, we should avoid allocating
the hw_id on that bit and restriction to bits [0:19] (i.e 20bits
instead of 21).
v2: Leave the max hw_id computation in i915_gem_context.c (Michel)
v3: Be consistent on if/else usage (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
BSpec: 1237
Reviewed-by: Michel Thierry <michel.thierry@intel.com >
Acked-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20180602112946.30803-2-lionel.g.landwerlin@intel.com
2018-06-04 18:12:54 +01:00
Chris Wilson
30aacd3fe7
drm/i915/gtt: Remove obsolete switch_mm hooks for gen8+
...
As the ppgtt for execlists is tightly coupled to the executing context,
and not switch separately, we no longer use the ppgtt->switch_mm hooks
on gen8+. Remove them.
References: 79e6770cb1chris@chris-wilson.co.uk >
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Matthew Auld <matthew.william.auld@gmail.com >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180604131552.29370-1-chris@chris-wilson.co.uk
2018-06-04 15:10:23 +01:00
Michal Wajdeczko
8979187a8c
drm/i915: Move i915_gem_fini to i915_gem.c
...
We should keep i915_gem_init/fini functions together for easier
tracking of their symmetry.
v2: rebased, pulled out from the series
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com >
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com >
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20180604090032.20840-1-michal.wajdeczko@intel.com
2018-06-04 15:00:01 +01:00
Arkadiusz Hiler
5428bf5a9a
drm/i915/icl: Calculate link clock using the new registers
...
Start using the new registers for ICL and on.
Cc: Manasi Navare <manasi.d.navare@intel.com >
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com >
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com >
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-13-paulo.r.zanoni@intel.com
2018-06-01 16:15:35 -07:00
Manasi Navare
51c83cfaf9
drm/i915/icl: Get DDI clock for ICL based on PLLs.
...
PLLs are the source clocks for the DDIs so in order
to determine the ddi clock we need to check the PLL
configuration.
This gets a little tricky for ICL since there is
no register bit that maps directly to the link clock.
So this patch creates a separate function in intel_dpll_mgr.c
to obtain the write array PLL Params and compares the set
pll_params with the table to get the corresponding link
clock.
v2:
- Fix the encoder type check (DK).
- Improve our error checking, return a sane value (Mika, Paulo).
- Fix table entries (Paulo).
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com >
Cc: Mika Kahola <mika.kahola@intel.com >
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com >
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com >
Reviewed-by: Mika Kahola <mika.kahola@intel.com >
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com >
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com >
[Paulo: implement v2]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180523224444.19017-1-paulo.r.zanoni@intel.com
2018-06-01 16:14:38 -07:00
Anusha Srivatsa
f17ca5010c
drm/i915/icl: Add Icelake PCH detection
...
This patch adds the support to detect PCH_ICP.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com >
Signed-off-by: Michel Thierry <michel.thierry@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-10-paulo.r.zanoni@intel.com
2018-06-01 16:14:26 -07:00
Radhakrishna Sripada
3937eb1a07
drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
...
On ICL we need to map VBT DDC Pin to BSpec DDC Pin.
Adding ICL Pin Values.
According to VBT
Block 2 (General Bytes Definition)
DDC Bus
+----------+-----------+--------------------+
| DDI Type | VBT Value | BSpec Mapped Value |
+----------+-----------+--------------------+
| DDI-A | 0x1 | 0x1 |
| DDI-B | 0x2 | 0x2 |
| PORT-1 | 0x4 | 0x9 |
| PORT-2 | 0x5 | 0xA |
| PORT-3 | 0x6 | 0xB |
| PORT-4 | 0x7 | 0xC |
+----------+-----------+--------------------+
Cc: James Ausmus <james.ausmus@intel.com >
Cc: Jani Nikula <jani.nikula@intel.com >
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com >
Cc: Clinton Taylor <clinton.a.taylor@intel.com >
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com >
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com >
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com >
Reviewed-by: James Ausmus <james.ausmus@intel.com >
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
[Paulo: checkpatch fixes.]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-9-paulo.r.zanoni@intel.com
2018-06-01 16:13:54 -07:00
