This adds the basic pin control muliplexing settings for the
Gemini SoC: parallel (NOR) flash, SATA, optional IDE, PCI and
UART.
We also select the right GPIO groups on all applicable systems
so that GPIO keys/LEDs work smoothly.
We can then build upon this for more complex systems.
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The macros for reset and clock lines were merged during the merge
window, this switches the Gemini to use these macros rather than
numerical defines.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the Faraday Technology FTDMAC020 DMA controller to
the Gemini SoC DTSI file. It is only used for memcpy work so
we can activate it for all users of the chipset.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We have a clock controller for the Gemini SoC, so make use of the
driver and add clocks to the peripherals. Remove the hard-coded
frequency from the UART and add switch the timer compatible to the
generic that uses the clock framework for clock speed look-up.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the Gemini reset controller to the Gemini SoC
DTSI file and also adds the reset references to all existing
blocks already in the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The binding should state "cortina,gemini-gpio", "faraday,ftgpio010"
stating the full name of the IP part.
Cc: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
