Hans de Goede
a97181adf1
clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clk
...
__clk_get_hw is supposed to be used by clk providers, not clk consumers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com >
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org >
Signed-off-by: Mike Turquette <mturquette@linaro.org >
2014-05-14 16:58:21 -07:00
Emilio López
95713978b0
clk: sunxi: Implement MMC phase control
...
HdG: add header exporting clk_sunxi_mmc_phase_control
Signed-off-by: Emilio López <emilio@elopez.com.ar >
Signed-off-by: Hans de Goede <hdegoede@redhat.com >
Signed-off-by: Mike Turquette <mturquette@linaro.org >
2014-05-05 15:55:57 -07:00
Sebastian Hesselbarth
be0804513a
clk: sunxi: declare OF clock provider
...
Common clock framework allows to register clock providers to get called
on of_clk_init() by using CLK_OF_DECLARE. This converts sunxi clock
providers to make use of it and get rid of the mach specific clk init
call. As sunxi has a bunch of independent clk provider nodes, we hook
current clock init to board compatible to make it called once.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com >
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com >
Acked-by: Mike Turquette <mturquette@linaro.org >
2013-09-29 21:07:16 +02:00
Emilio López
e874a66977
clk: arm: sunxi: Add a new clock driver for sunxi SOCs
...
This commit implements the base CPU clocks for sunxi devices. It has
been tested using a slightly modified cpufreq driver from the
linux-sunxi 3.0 tree.
Additionally, document the new bindings introduced by this patch.
Idling:
/ # cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc32k 0 0 32768
osc24M_fixed 0 0 24000000
osc24M 0 0 24000000
apb1_mux 0 0 24000000
apb1 0 0 24000000
pll1 0 0 60000000
cpu 0 0 60000000
axi 0 0 60000000
ahb 0 0 60000000
apb0 0 0 30000000
dummy 0 0 0
After "yes >/dev/null &":
/ # cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc32k 0 0 32768
osc24M_fixed 0 0 24000000
osc24M 0 0 24000000
apb1_mux 0 0 24000000
apb1 0 0 24000000
pll1 0 0 1008000000
cpu 0 0 1008000000
axi 0 0 336000000
ahb 0 0 168000000
apb0 0 0 84000000
dummy 0 0 0
Signed-off-by: Emilio López <emilio@elopez.com.ar >
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com >
Signed-off-by: Mike Turquette <mturquette@linaro.org >
2013-03-27 08:35:34 -07:00
Prashant Gaikwad
85a181986c
clk: sunxi: Use common of_clk_init() function
...
Use common of_clk_init() function to initialize clocks.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com >
Acked-by: Maxime Ripard <maxime.ripard@anandra.org >
Signed-off-by: Mike Turquette <mturquette@linaro.org >
2013-01-24 11:12:23 -08:00
Maxime Ripard
404525d5a7
clk: sunxi: Add dummy fixed rate clock for Allwinner A1X SoCs
...
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com >
Cc: Mike Turquette <mturquette@ti.com >
2012-11-16 21:46:39 +01:00
